Hi,
On 02.09.2017 21:02, Nicola Corna wrote:
September 2, 2017 5:39 PM, "Nico Huber" nico.h@gmx.de wrote:
From the original op menu these are probably unneeded: byte program (0x02), either one of the block erasers (0x20 and 0xd8) and the fast read (0x0b).
Probably working (with flashrom) op menu for your chip:
0x05030201 0x04ad9f20
I've modified the OPMENU 6 and 7 in sb/intel/bd82x6x/pch.h with this
#define SPI_OPMENU_6 0xad /* AAI write */ #define SPI_OPTYPE_6 0x01 /* Write, no address */
#define SPI_OPMENU_7 0x04 /* Write disable */ #define SPI_OPTYPE_7 0x01 /* Write, no address */
and indeed it works now.
There's only one thing that I don't understand: why is it preferable to modify the allowed op codes in coreboot instead of modifying the default write mode for the SST25VF032B in flashrom? From its datasheet I see that it supports the usual byte-program mode in addition to the AAI mode.
TLDR; it would be a lot slower.
Alas, there is no usual byte-program mode. Most chips do a 256B page program which uses op code 0x02 too. For the SST25VF032B it's really a 1B program. If you use that instead of the AAI write, you get lots of overhead (6B total, if I'm not mistaken, instead of ~1.5B per actual written byte + twice the polling for write-in-progress).
Nico