Scott Duplichan [mailto:scott@notabs.org] wrote:
[...]
]As for the mouse problem, I think it may be PIC interrupt ]routing related. I see our PIR table is incomplete and also ]the legacy interrupting route reporting registers in PCI ]config space are not filled in. I will look at that tomorrow.
I got the USB mouse working by setting up the PIC interrupt routing and reporting. For now the changes are in mptable.c. They may need to be relocated to a better place. The NIC bus number is hard-coded at the moment. This needs fixing if the NIC bus number can change.
KolibriOS reads PCI config offset 3C to find PIC interrupt routing, so these must be filled in. The same values must be programmed into the SB800 PIC mode interrupt routing registers. In addition, a change to the legacy mode edge-level control register setting is needed. An updated archive is here: http://notabs.org/coreboot/e350m1-kolibri-001.7z
An mptable.c patch is attached.
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 6444be5..b6c5b76 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -35,6 +35,7 @@ extern u32 apicid_sb800; extern u32 bus_type[256]; extern u32 sbdn_sb800;
+// SB800 interrupt routing register values: APIC mode u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ @@ -45,6 +46,16 @@ u8 intr_data[] = { 0x10,0x11,0x12,0x13 };
+// SB800 interrupt routing register values: PIC mode +u8 intr_data_pic[] = { + 0x0B, 0x0A, 0x0B, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F, // 0x00 + 0x00, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, // 0x08 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x10 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x18 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x20 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x28 + 0x0B, 0x0A, 0x0B, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F}; // 0x30 + static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -75,6 +86,12 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
+ // progran the SB800 PIC mode interrupt routing register values + for (byte = 0x0; byte < sizeof(intr_data_pic); byte ++) { + outb(byte, 0xC00); + outb(intr_data_pic[byte], 0xC01); + } + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -149,6 +166,25 @@ static void *smp_write_config_table(void *v) IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */
+ // program interrupt line registers for legacy OS use + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x01, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x01, 1)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x04, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x11, 0)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x12, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x12, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x13, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x13, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 1)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 2)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 5)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x16, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x16, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(3, PCI_DEVFN(0x00, 0)), 0x3C, 0x0B); + + // program slave PIC edge-level control register + outb (0x0C, 0x4D1); + /* Compute the checksums */ return mptable_finalize(mc); }
Thanks, Scott