The script didn't help. Seabios just doesn't see the rom. Is this a seabios problem? I didn't have this problem for the tyan s2881. Here is the output again:
PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000 Incorrect Expansion ROM Header Signature 0000 Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 5 resources PCI: 00:18.0: enabled 1, 4 resources PCI: 01:01.0: enabled 1, 3 resources PCI: 01:01.1: enabled 1, 1 resources PCI: 01:02.0: enabled 0, 0 resources PCI: 01:02.1: enabled 1, 1 resources PCI: 01:03.0: enabled 1, 3 resources PCI: 04:00.0: enabled 1, 1 resources PCI: 04:00.1: enabled 1, 1 resources PCI: 04:00.2: enabled 0, 0 resources PCI: 04:01.0: enabled 0, 0 resources PCI: 04:06.0: enabled 1, 4 resources PCI: 01:04.0: enabled 1, 3 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 3 resources PNP: 002e.2: enabled 0, 4 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.4: enabled 0, 2 resources PNP: 002e.5: enabled 0, 1 resources PNP: 002e.6: enabled 1, 3 resources PNP: 002e.7: enabled 0, 2 resources PNP: 002e.8: enabled 0, 2 resources PNP: 002e.9: enabled 0, 2 resources PNP: 002e.a: enabled 0, 2 resources PCI: 01:04.1: enabled 1, 1 resources PCI: 01:04.2: enabled 1, 1 resources PCI: 01:04.3: enabled 1, 1 resources I2C: 01:70: enabled 1, 0 resources I2C: 00:2c: enabled 1, 0 resources I2C: 01:50: enabled 1, 0 resources I2C: 01:51: enabled 1, 0 resources I2C: 01:52: enabled 1, 0 resources I2C: 01:53: enabled 1, 0 resources I2C: 01:54: enabled 1, 0 resources I2C: 01:55: enabled 1, 0 resources I2C: 01:56: enabled 1, 0 resources I2C: 01:57: enabled 1, 0 resources PCI: 01:04.5: enabled 0, 0 resources PCI: 01:04.6: enabled 1, 2 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 1 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources APIC: 01: enabled 1, 0 resources PCI: 02:03.0: enabled 1, 2 resources PCI: 02:04.0: enabled 1, 2 resources Initializing CBMEM area to 0x3fff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 3fff0200...ok High Tables Base is 3fff0000. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x3fff0400... done. PIRQ table: 176 bytes. Looking for bad PCIX MHz input Looking for bad Hot Swap Enable OK 133MHz & Hot Swap is off Wrote the mp table end at: 000f0410 - 000f0614 Adding CBMEM entry as no. 3 Looking for bad PCIX MHz input Looking for bad Hot Swap Enable OK 133MHz & Hot Swap is off Wrote the mp table end at: 3fff1410 - 3fff1614 MP table: 532 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 9bdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3fff2400 rom_table_end = 0x3fff2400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3fff2400 to 0x40000000 Adding high table area Wrote coreboot table at: 3fff2400 - 3fff2ca4 checksum b5b9 coreboot table: 2212 bytes. 0. FREE SPACE 3fff4400 0000bc00 1. GDT 3fff0200 00000200 2. IRQ TABLE 3fff0400 00001000 3. SMP TABLE 3fff1400 00001000 4. COREBOOT 3fff2400 00002000 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + a590 + align -> fff8a600 Check fallback/payload Got a payload Loading segment from rom address 0xfff8a638 data (compression=1) malloc Enter, size 36, free_mem_ptr 00160ce4 malloc 00160ce4 New segment dstaddr 0xf0000 memsize 0x10000 srcaddr 0xfff8a670 filesize 0x7350 (cleaned up) New segment addr 0xf0000 size 0x10000 offset 0xfff8a670 filesize0 Loading segment from rom address 0xfff8a654 Entry Point 0x000fc4f3 Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x00 lb: [0x0000000000100000, 0x0000000000164000) Post relocation: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x00 using LZMA [ 0x00000000000f0000, 0000000000100000, 0x0000000000100000) <- 00000000fff8a670 dest f0000, end 100000, bouncebuffer 7ff38000 Loaded segments Jumping to boot code at fc4f3 entry = 0x000fc4f3 lb_start = 0x00100000 lb_size = 0x00064000 adjust = 0x7fe9c000 buffer = 0x7ff38000 elf_boot_notes = 0x00113a20 adjusted_boot_notes = 0x7ffafa20 Start bios (version 0.4.2-20090908_202836-morn.localdomain) CPU Mhz=1804 Found mainboard Arima HDAMA Found CBFS header at 0xfffeffe0 Ram Size=0x80000000 Found 2 cpu(s) Scan for VGA option rom Got ps2 nak (status=51); continuing ps2_recvbyte timeout Found 0 lpt ports Found 1 serial ports Copying PIR from 0x3fff0400 to 0x000fdc50 Copying MPTABLE from 0x3fff1400/3fff1410 to 0x000fda30 SMBIOS ptr=0x000fda10 table=0x7ffff800
Scan for option roms Press F12 for boot menu.
Returned 61440 bytes of ZoneHigh e820 map has 7 items: 0: 0000000000000000 - 000000000009f400 = 1 1: 000000000009f400 - 00000000000a0000 = 2 2: 00000000000f0000 - 0000000000100000 = 2 3: 0000000000100000 - 000000003fff0000 = 1 4: 000000003fff0000 - 0000000040000000 = 2 5: 0000000040000000 - 000000007ffff000 = 1 6: 000000007ffff000 - 0000000080000000 = 2 enter handle_19: NULL Booting from Floppy... fail handle_legacy_disk:845(1): a=00000201 b=00000000 c=00000001 d=00000000 ds=0000 es=07c0 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00007b18 cs=f000 ip=e82d f=0002 Boot failed: could not read the boot disk
enter handle_18: NULL Booting from CD-Rom... Boot failed: Could not read from CDROM (code 0001) enter handle_18: NULL Booting from Hard Disk... fail handle_legacy_disk:845(1): a=00000201 b=00000000 c=00000001 d=00000080 ds=0000 es=07c0 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00007b18 cs=f000 ip=e82d f=0002 Boot failed: could not read the boot disk
enter handle_18: NULL Booting from CBFS... enter handle_18: NULL No bootable device.
CTRL-A Z for help |115200 8N1 | NOR | Minicom 2.3 | VT102 | Offline