detection is the same on most chipsets (if not all) especially if it comes to EDO/FPM detection.
Can't SPD data just be used to do that?
there is no SPD for EDO/FPM rams so testing would be the only way to determine size and type (and chipsets have special functions to do that). even if there is SDRAM we still could have problems reading it if we don't know on which GPIOs clk/data is connected.
Size and type detection definitely wont work without SPD-ROMs for SDRAM and all kinds of DDR.
we still could run into problems on sdrams with wrong SPD data. some very cheap modules came with incorrect data programmed into the SPD chips. but the main reason is that there are mainboards that might not provide SPD data since we don't know where the clk/data lines are connected.
On DDR we use SPD for everything. Why do you say it should not be used for sizes ?
it should only be used for fallback if we can't (yet) obtain any SPD data.
still a question remains: should we add overclocking options somewhere? maybe in the config file?
First thought: No.
Second thought: If it does not waste the algorithms and keeps them readable. Why not..
the timing information would just be inserted into the data read by the dram detection algorithm. though i still don't know if i would implement timing detection into the dram detection algorithm. as i already wrote: no SPD on EDO/FPM, so speed detection would be writing, reading back and comparing.
btw. a generic dram detection mechanism for EDO, FPM and SDR would look kinda like this:
1. set dram type to EDO 2. set dram size to max. chipset supports 3. set dram addressing scheme to std. 4. write D1=0x5555555555555555 to A0=0x0 5. write D2=0xaaaaaaaaaaaaaaaa to A8=0x8 6. enable EDO detection (chipset feature) 7. read back data at A0 8. compare result to D1. if unequal goto 12 9. read back data at A8 10. compare result to D2. if unequal goto 12 11. dram type is EDO :) 12. dram type is FPM or SDR
now there are some more checks that determine the real size of the EDO ram (remember: we assumed that it is max. chipset supports) and the correct addressing scheme.