Hi Mahmut,
I no longer work on this, don`t known current code status and can`t check if it is related to your issue or not but from your log:
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [ERROR] SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x800000!!
When I last worked on this board CONFIG_ROM_SIZE should be set to real/physical size of your flash chip (guessing 0x1000000 = 16M) And CONFIG_CBFS_SIZE (writing from my memory) to expected coreboot image size i.e. 0x800000 (8M)
After building it will give you 16M image then you need to extract coreboot part (last 8M) and flush it to top of flash address space (or use other methods to build full image)
Mariusz
-----Original Message----- From: Paul Menzel pmenzel@molgen.mpg.de Sent: Wednesday, December 21, 2022 2:28 PM To: coreboot@coreboot.org Cc: Eusebio, Vanessa F vanessa.f.eusebio@intel.com Subject: [coreboot] Re: Unexpected Exception on Intel Harcuvar CRB (Intel Denverton-NS SoC) with coreboot 4.16
Dear Mahmut,
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Am 21.12.22 um 13:37 schrieb Mahmut Olger via coreboot:
We are using intel atom C3558 denverton_NS platform. This platform is booting with coreboot4.16.
Welcome.
Payload of coreboot is Seabios. Openbsd running in our board. Sometimes occur unexpected exception. You can find all coreboot and exception log above and you can find coreboot .config file. What is cause that exception. How can I solve it.
Stabbing in the dark, I’d suggest to test latest code first, so build from the master branch.
I am adding the maintainers to Cc. Maybe they have an idea.
Kind regards,
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