Author: stepan Date: Thu Apr 22 12:44:08 2010 New Revision: 5476 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5476
Log: None of the cs5536 settings in devicetree.cb were ever used and nobody noticed. Fix it!
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/src/include/cpu/amd/gx2def.h trunk/src/southbridge/amd/cs5536/cs5536.c
Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Thu Apr 22 11:22:15 2010 (r5475) +++ trunk/src/include/cpu/amd/gx2def.h Thu Apr 22 12:44:08 2010 (r5476) @@ -693,4 +693,11 @@ #define PMLogic_BASE ( 0x9D00)
+#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if defined(__PRE_RAM__) +#else +void cpubug(void); +#endif +#endif + #endif /* CPU_AMD_GX2DEF_H */
Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Thu Apr 22 11:22:15 2010 (r5475) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Thu Apr 22 12:44:08 2010 (r5476) @@ -527,10 +527,24 @@ device_t dev; msr_t msr; u32 msrnum; - struct southbridge_amd_cs5536_config *sb = - (struct southbridge_amd_cs5536_config *)dev->chip_info; + struct southbridge_amd_cs5536_config *sb; struct msrinit *csi;
+ dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_ISA, 0); + + if (!dev) { + printk(BIOS_ERR, "CS5536 not found.\n"); + return; + } + + sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; + + if (!sb) { + printk(BIOS_ERR, "CS5536 configuration not found.\n"); + return; + } + post_code(P80_CHIPSET_INIT);
/* we hope NEVER to be in coreboot when S3 resumes @@ -599,6 +613,12 @@ */
printk(BIOS_ERR, "cs5536: %s\n", __func__); + + if (!sb) { + printk(BIOS_ERR, "CS5536 configuration not found.\n"); + return; + } + setup_i8259(); lpc_init(sb); uarts_init(sb);