On Wed, Nov 16, 2022 at 9:23 AM Martin Roth via coreboot coreboot@coreboot.org wrote:
The current state of the coreboot postcodes is a mess. There’s no good way to give anyone a postcode table. The post_code() function is called with direct hardcoded values all over the codebase. The post_codes.h file is disorganized with values being added without regard for being contiguous or ordered. As an example, despite using hexadecimal values, console post codes go from 0x39 to 0x40.
A while ago I did look into the topic of post codes a bit and wrote a script to summarize all usages of post_code(), the post code macros, and usages of raw hex values. I've since tweaked it and have uploaded a patch to Gerrit [1]. Hopefully it will help track down where and what postcodes are currently used throughout the tree. Also of note is that there are a number of post code macros in src/soc/amd/common/psp_verstage/include/psp_verstage.h, which also sometimes conflict with other codes (something made very clear in the output of my script)
Proposed postcode ranges
* 0x00 : unregulated - 0x00 is not a good postcode. * * 0x01 - 0x07 : coreboot startup code & common * 0x08 - 0x0b : coreboot console * 0x0c - 0x0f : <RESERVED> * * 0x10 - 0x1f : coreboot bootblock * 0x20 - 0x2f : coreboot romstage * 0x30 - 0x33 : postcar * 0x34 - 0x3f : coreboot ramstage * 0x40 - 0x4f : coreboot ramstage hardwaremain boot stages * * 0x50 - 0x5f : Mainboard specific - Each mainboard can use as it chooses * 0x60 - 0x6f : SOC specific - Each SoC/CPU/Chipset can use as it chooses * * 0x70 : Driver/SuperIO ID, followed by ID byte * 0x71 - 0x7f : Driver/SuperIO specific - Can use as the device chooses * * 0x80 - 0x87 : ACPI postcodes * 0x88 - 0x8f : Unregulated - may be used anywhere for any purpose. * 0x90 - 0x9f : Vendorcode calls: FSP, AGESA, etc. * * 0xa0 - 0xaf : <RESERVED> * 0xb0 - 0xbf : <RESERVED> * * 0xc0 - 0xca : <RESERVED> * * 0xcb : coreboot identifier - used when returning from FSP, AGESA, etc * * 0xcc - 0xcf : <RESERVED> * * 0xd0 - 0xdf : Debug postcodes - never enabled by default. * * 0xe0 - 0xef : Errors * 0xf0 - 0xf7 : SMM * 0xf8 - 0xfe : end of coreboot code - resume and the like. * 0xff : coreboot finished - jump to payload
FSP does seem to have some of its own internal multibyte post codes (refer to the FSP integration guides) so that might conflict with these ranges, but I guess post codes issued by coreboot before and after an FSP call would help differentiate these.
Sindhoor Tilak also seems to have done some work on post codes a few years ago [2], though it may not apply to the current state of the tree and probably now has post code values that conflict with Martin's suggestions.
Cheers, Nicholas
[1] https://review.coreboot.org/c/coreboot/+/69712 [2] https://review.coreboot.org/q/owner:sindhoor%2540sin9yt.net