Vikram Narayanan (vikram186@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/507
-gerrit
commit c2a8f4b71c767287ab34df8455fc5f3848dcf5c6 Author: Vikram Narayanan vikram186@gmail.com Date: Sat Jan 14 14:36:51 2012 +0530
APIC: Fixed reading MSR_FSB_FREQ register
According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB frequency. But the code had a right shift of 4 which will always give 267 MHz, as the valid bits are shifted to right.
Change-Id: I6bf93bac1ee9123af78c003f5a0728f8f0801958 Signed-off-by: Vikram Narayanan vikram186@gmail.com --- src/cpu/x86/lapic/apic_timer.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 826f5b6..0b56fd5 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -28,6 +28,7 @@ */
#define FSB_CLOCK_STS 0xcd +#define FSB_FREQ_MASK 0x07
static u32 timer_fsb = 200; // default to 200MHz
@@ -46,7 +47,7 @@ void init_timer(void)
/* Set FSB frequency to a reasonable value */ fsb_clock_sts = rdmsr(FSB_CLOCK_STS); - switch ((fsb_clock_sts.lo >> 4) & 0x07) { + switch (fsb_clock_sts.lo & FSB_FREQ_MASK) { case 0: timer_fsb = 266; break; case 1: timer_fsb = 133; break; case 2: timer_fsb = 200; break;