ron minnich wrote:
This is closer, I worked out the short-circuit-between-my-ears problem a bit further.
But it hangs at post A0.
ron
This stuff looks fine but I didn't build or run it.
Take a look in artecgroup\dbe61. There is some code to print_debug the memory registers at the end of cache_as_ram_main.
So 0xA0 is POST_PLL_INIT. My guess is either a. manualconf is set and PLLMSRhi PLLMSRlo are bad values b. the hardware strap settings are not set. This would be a jumper setting. If it is hardwired on the board and it is not correct you need to setup manualconf.
Marc