Only probe for chips with compatible bus protocols. It doesn't make sense to probe for SPI chips on a LPC host, nor does it make sense to probe for LPC chips on a Parallel host.
This change is backwards compatible, but adding host protocol info to chipset init functions will speed up probing.
Once all chipset init functions are updated and the Winbond W29EE011 and AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can be deleted as the W29/A49 conflict magically disappears.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: flashrom-chiptype_avoid_bus_mismatch/it87spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Arbeitskopie) @@ -109,14 +109,23 @@
int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; }
int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; }
/* Index: flashrom-chiptype_avoid_bus_mismatch/nic3com.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Arbeitskopie) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
+ buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; }
Index: flashrom-chiptype_avoid_bus_mismatch/satasii.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/satasii.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/satasii.c (Arbeitskopie) @@ -67,6 +67,9 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar)) & (1 << 26))) printf("Warning: Flash seems unconnected.\n");
+ /* Not sure if it only speaks Parallel. */ + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; }
Index: flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Arbeitskopie) @@ -63,6 +63,7 @@ return 1;
printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Arbeitskopie) @@ -29,6 +29,8 @@ int dummy_init(void) { printf_debug("%s\n", __func__); + /* This depends on UNKNOWN having all bits set. */ + buses_supported = CHIP_BUSTYPE_UNKNOWN; spi_controller = SPI_CONTROLLER_DUMMY; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Arbeitskopie) @@ -36,13 +36,12 @@ unsigned long flashbase = 0;
/** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */
-enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI;
extern int ichspi_lock;
@@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c));
+ /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes();
@@ -262,22 +263,29 @@ */
if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; }
switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; }
- if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + }
/* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Index: flashrom-chiptype_avoid_bus_mismatch/flashrom.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) @@ -188,6 +188,10 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + printf_debug("skipped. Host and chip bus type are incompatible.\n"); + continue; + }
size = flash->total_size * 1024;