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On 03/02/2017 01:30 PM, Arthur Heymans wrote:
Paul Menzel via coreboot coreboot@coreboot.org writes:
I think most of the time is spent in RAM initialization.
- Do board owners with similar amount of memory (independent of the board) have similar numbers?
- What are the ways to improve that? Is it possible? For example, can the modules be probed in parallel (if that isn’t done already)?
I'm not the right person to answer this since I don't know this code/hardware that well, but on modern Intel hardware native code uses the MRC cache to store dram training results and restore those on next boots (and resume from suspend) if no change in dimm configuration was detected.
Maybe something like this could also be applied here (or maybe it's already the case since it includes code to access spi flash)?
Yes, this is already implemented as an option, and it does a fairly decent job of reducing training overhead to almost nothing, but the ECC clear overhead remains. Ideally both training and ECC clear would be parallelized, but as before romstage is a very limited environment and I'm not sure the cost / benefit ratio is there to implement this feature right now. I'd feel somewhat more confident if there was more support for parallel tasking in coreboot in general, instead of having to create a northbridge-specific system like the old K8 raminit.
- -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com