Author: myles Date: 2009-10-14 04:38:24 +0200 (Wed, 14 Oct 2009) New Revision: 4771
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Log: Use CAR ck804 code with the s2892. Reset the s2891 so the HT speed gets updated. Remove some PANTA comments. Add SATA init from non-CAR version.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-10-13 22:53:24 UTC (rev 4770) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-10-14 02:38:24 UTC (rev 4771) @@ -222,8 +222,8 @@ needs_reset |= ck804_early_setup_x();
if (needs_reset) { - print_info("ht reset -\r\n"); - // soft_reset(); + printk_info("ht reset -\r\n"); + soft_reset(); }
allow_all_aps_stop(bsp_apicid);
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-10-13 22:53:24 UTC (rev 4770) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-10-14 02:38:24 UTC (rev 4771) @@ -75,7 +75,7 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
-#include "southbridge/nvidia/ck804/ck804_early_setup.c" +#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
#include "cpu/amd/car/copy_and_run.c"
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2009-10-13 22:53:24 UTC (rev 4770) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2009-10-14 02:38:24 UTC (rev 4771) @@ -164,6 +164,18 @@
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
+ /* Activate master port on primary SATA controller. */ + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, @@ -177,7 +189,7 @@
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
-// PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
@@ -251,8 +263,9 @@
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
-//PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
+/* This line doesn't exist in the non-CAR version. */ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), @@ -292,10 +305,10 @@ io_base[j] + ANACTRL_IO_BASE + 0xb4, io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); -//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, -// io_base[j] + ANACTRL_IO_BASE + 0xc4, -// io_base[j] + ANACTRL_IO_BASE + 0xc8, -// cpu_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, + io_base[j] + ANACTRL_IO_BASE + 0xc4, + io_base[j] + ANACTRL_IO_BASE + 0xc8, + cpu_ss_tbl, 64); } }