Hi,
I have/know only 10 years old boards.
usually it is not mapped to anywhere. Some older superIO chips (ITE) supported to dump the values to the LPT port. There are cheap POST cards which can be plugged into ISA, PCI or PCIe slots, but a least in the case of PCIe I don't think they decodes PCIe IO. LPC header could be probably used for that purpose.
From the architecture point of view I think port 80h was just a regular IO which was guaranteed to not be used, so they used it for delay loops and later they made a POST port from it (BIOS just writes a ID value of the current state of the boot).
Petr
Dne 16. 10. 19 v 14:35 Jorge Fernandez Monteagudo napsal(a):
Hi all,
Sorry for my noob question but, how can I know where the IO port 80 is physically mapped in my hardware?
I have a custom board with an AMD Prairie Falcon SOC and I'm still trying to get it work. I've read the AGESA blob could post error codes to this IO port and I would like to get this info, but I don't complete understand the magic behind the postcodes and the IO port. Anybody could bring some light?
Regards Jorge _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org