Postcodes to IO port 80

[Jorge Fernandez Monteagudo]

Hi all,

Sorry for my noob question but, how can I know where the IO port 80 is physically mapped in my hardware?

I have a custom board with an AMD Prairie Falcon SOC and I'm still trying to get it work. I've read the AGESA
blob could post error codes to this IO port and I would like to get this info, but I don't complete understand the
magic behind the postcodes and the IO port. Anybody could bring some light?

Regards
Jorge

[Petr Cvek]

Hi,

I have/know only 10 years old boards.

usually it is not mapped to anywhere. Some older superIO chips (ITE) supported to dump the values to the LPT port. There are cheap POST cards which can be plugged into ISA, PCI or PCIe slots, but a least in the case of PCIe I don't think they decodes PCIe IO. LPC header could be probably used for that purpose.

From the architecture point of view I think port 80h was just a regular IO which was guaranteed to not be used, so they used it for delay loops and later they made a POST port from it (BIOS just writes a ID value of the current state of the boot).

Petr

Dne 16. 10. 19 v 14:35 Jorge Fernandez Monteagudo napsal(a):
> Hi all,
>
> Sorry for my noob question but, how can I know where the IO port 80 is physically mapped in my hardware?
>
> I have a custom board with an AMD Prairie Falcon SOC and I'm still trying to get it work. I've read the AGESA
> blob could post error codes to this IO port and I would like to get this info, but I don't complete understand the
> magic behind the postcodes and the IO port. Anybody could bring some light?
>
> Regards
> Jorge
> _______________________________________________
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> To unsubscribe send an email to [e-mail]

[Sergej Ivanov]

Hello.

Port 80h usually usable only on old boards with native PCI (not PCIe)
buses, even if your board has PCI slot it is usually uses PCIe to PCI
bridge chip. It won't get thru any of PCI Bridges, so it's unusable in PCIe
system(each PCIe slot is passed via individual PCI Bridge). For debugging
purposes try to use LPC Post Card and enable corresponding Coreboot option.

[Kyösti Mälkki]

On Wed, Oct 16, 2019 at 3:36 PM Jorge Fernandez Monteagudo
<[e-mail]> wrote:
> Hi all,
>
> Sorry for my noob question but, how can I know where the IO port 80 is physically mapped in my hardware?
>
> I have a custom board with an AMD Prairie Falcon SOC and I'm still trying to get it work. I've read the AGESA
> blob could post error codes to this IO port and I would like to get this info, but I don't complete understand the
> magic behind the postcodes and the IO port. Anybody could bring some light?

Do you have working coreboot serial console and postcodes already?
Recent AMD SoCs have LPC clocks disabled and/or LPC pins as
multi-purpose. See hudson_lpc_port80() implementation and try adapt
from that to route IO 0x80 to LPC.

You can contact me privately if you are willing to share more details
from your design.

Regards,
Kyösti Mälkki

[Jorge Fernandez Monteagudo]

Hi all, thanks for your answers!
> Do you have working coreboot serial console and postcodes already?
> Recent AMD SoCs have LPC clocks disabled and/or LPC pins as
> multi-purpose. See hudson_lpc_port80() implementation and try adapt
> from that to route IO 0x80 to LPC.

Yes, the serial console is working and I can see the post codes in the console. But I lost the
trace once the code calls 'amd_init_post()' in the agesawrapper.c. I've read that the code
sends POST codes and I was wondering if any is sent from that code. 
My board uses the stoneyridge AMD SOC and I've found that 'lpc_enable_port80()' is called
by default on 'bootblock_fch_early_init()' from southbridge.c... I'll try to get something from
the LPC.

Thanks again!
Jorge