Re: [coreboot] m57sli-s4 flashrom regression for v1(.1) boards (plcc) since r2972

[Carl-Daniel Hailfinger]

On 01.02.2008 22:46, Ward Vandewege wrote:
> So; r2972 introduced two patches with this comment:
>
> ==========================================================================
>
> r2972 | hailfinger | 2007-11-14 10:09:30 -0500 (Wed, 14 Nov 2007) | 17 lines
>
> Autodetect presence of serial flash and set up the board accordingly.
> This enables us to have only one configuration and one set of code for
> all revisions of the Gigabyte GA-M57SLI-S4.
> Flash is now setup correctly for both SPI and LPC flash.
>
> Detection of SPI flash in flashrom on rev. 2.x boards now hangs
> instead of failing. However, that is just an effect of the combination
> of incomplete initialization of the SPI controller and paranoid checks
> in the flashrom SPI code.
> If anyone wants to work on that, he needs a logic analyzer or creative
> imagination. Hint: LPC-to-SPI read passthrough, clock signal.
>
> Remaining issues for the M57SLI: Fan/environment control.
>
> Signed-off-by: Carl-Daniel Hailfinger 
> Acked-by: Harald Gutmann
>
> ==========================================================================
>
> One of those patches breaks flashrom on rev 1 and 1.1 of the m57sli (that's
> the plcc version of the board):
> Index: src/mainboard/gigabyte/m57sli/Config.lb
>
> --- src/mainboard/gigabyte/m57sli/Config.lb     (revision 2955)
> +++ src/mainboard/gigabyte/m57sli/Config.lb     (revision 2972)
> @@ -310,7 +310,7 @@
>                                         # SIO pin set 1 input mode
>                                                                 #irq 0xc8 = 0x0
>                                         # SIO pin set 2 mixed input/output
>                                         # mode
>                                                           irq 0xc9 = 0x0
>                                                           irq 0xc9 = 0x40
>                                   # SIO pin set 4 input mode
>                                                           #irq 0xcb = 0x0
>                                   # Generate SMI# on EC IRQ
>
> Reversing this hunk fixes flashrom on the plcc version of our board.

I had one similar report from another user of rev 1.x of the board. The
change slipped in, it was there to reduce differences on  rev 2.x
boards, but it turned out that it was not related to the flashrom issues
and will cause flashing on rev 1.x to fail.
> If it turns out that this value needs to be different for the various
> revisions of the m57sli, any thoughts on how we are going to handle that?
>
> Carl-Daniel - this hunk seems somewhat unrelated to the log message and the
> other part of r2972; do you remember what exactly it was for?

See above. Could you send a patch to revert it and change the comment
above the reverted line to
"SIO pin set 2 input mode"

Such a patch is acked in advance.
Acked-by: Carl-Daniel Hailfinger

Regards,
Carl-Daniel