Stefan Reinauer stepan@suse.de writes:
Hi,
I still don't get the 8151 to work properly on the solo board.
i believe that the link setup looks like:
Athlon64 | 8151 | 8111since athlon64 has only one ht link.
Yes. And that is also how AMD schematic show it.
my config.lb defines: northbridge amd/amdk8 "mc0" southbridge amd/amd8151 "amd8151" link 0 end southbridge amd/amd8111 "amd8111" link [1|2] end end
What is the right way of describing how the 8111 is connected in the config?
So far I pretend a hypertransport chain is just a bus so the amd 8111 hangs off of link 0 of mc0.
And I only get hangs at:
NB: Function 3 Misc Control..
IF I set amd8111 link to 0 I get a reboot plus hang at PCI: 03:00.2 [ffff/ffff] disabled
It might be an interesting test case not to disable anything, in the config file..
amd8111_enable dev: PCI: 03:01.0 lpc_dev: PCI: 01:05.0 index: 9 reg: fe9f -> fce
This bit looks decidedly weird. I would expect the 8111 lpc device to show up at 01:04.0. And it shows up at 01:5 odd but ok. I guess bus 2 goes to the agp. And then bus 3 would go to the pci buss hanging off the amd8111. So 3:0.0 makes sense to be the pci device hanging off there.
The really weird part is that the disable is clearing multiple enable bits and that does not feel correct somehow.
PCI: 03:01.0 [ffff/ffff] disabled
PCI: 03:05.0 [14e4/1645] enabled
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
And this feels like memory corruption. I wonder if I broke the unbuffered dimm case?
LinuxBIOS-1.1.5.0-Fallback Mo Okt 20 11:35:43 CEST 2003 rebooting...
I also noticed that not all elements in the capability linked list of the 8151 are HT capabilities. The first one on 8151 is an AGP capability element. Maybe this explains why a different ordered probing is needed, does LinuxBIOS correctly skip AGP capability blocks?
It should ignore all but HT capabilities bugs are possible.
BTW I need to find a way to cleanly handle bugs in capabilities.
Eric