Re: [coreboot] [PATCH] [flashrom] ICH7 SPI support

[Peter Stuge]

On Fri, Jun 27, 2008 at 05:44:51PM +0200, Stefan Reinauer wrote:
> ICH7 SPI support
> fix some variable names in ichspi.c (Offset -> offset)
> Dump ICH7 SPI bar with -V
> Improve error message in case IOPL goes wrong. (It might not even be an IOPL)
>
> Signed-off-by: Stefan Reinauer

Acked-by: Peter Stuge
> Index: flash.h
>
> --- flash.h	(revision 3392)
> +++ flash.h	(working copy)
> @@ -370,6 +370,7 @@
>  /* chipset_enable.c */
>  int chipset_flash_enable(void);
>  void print_supported_chipsets(void);
> +extern int ich7_detected;
>  extern int ich9_detected;
>  extern void *ich_spibar;
> Index: spi.c
>
> --- spi.c	(revision 3392)
> +++ spi.c	(working copy)
> @@ -2,6 +2,7 @@
> This file is part of the flashrom project.
> Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
> Copyright (C) 2008 coresystems GmbH
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
>
> @@ -35,6 +36,8 @@
>  {
>    if (it8716f_flashport)
>    	return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
>   else if (ich7_detected)
>           return ich_spi_command(writecnt, readcnt, writearr, readarr);
> else if (ich9_detected)
>   return ich_spi_command(writecnt, readcnt, writearr, readarr);
>  printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
>
> @@ -357,6 +360,8 @@
>  {
>    if (it8716f_flashport)
>    	return it8716f_spi_chip_read(flash, buf);
>   else if (ich7_detected)
>           return ich_spi_read(flash, buf);
> else if (ich9_detected)
>   return ich_spi_read(flash, buf);
>  printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
>
> @@ -367,6 +372,8 @@
>  {
>    if (it8716f_flashport)
>    	return it8716f_spi_chip_write(flash, buf);
>   else if (ich7_detected)
>           return ich_spi_write(flash, buf);
> else if (ich9_detected)
>   return ich_spi_write(flash, buf);
>  printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
> Index: chipset_enable.c
>
> --- chipset_enable.c	(revision 3392)
> +++ chipset_enable.c	(working copy)
> @@ -189,15 +189,16 @@
>
> static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar)
>  {
> uint8_t old, new, bbs;
>
> uint8_t old, new, bbs, buc;
> uint32_t tmp, gcs;
> void *rcrb;
>
> /* Read the Root Complex Base Address Register (RCBA) */
> tmp = pci_read_long(dev, 0xf0);
>
> /* Calculate the Root Complex Register Block address */
>  tmp &= 0xffffc000;
> printf_debug("Root Complex Register Block address = 0x%x\n", tmp);
> printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
> rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp);
> if (rcrb == MAP_FAILED) {
> perror("Can't mmap memory using " MEM_DEV);
>
> @@ -212,11 +213,42 @@
>    printf_debug("BOOT BIOS Straps: 0x%x (%s)\n",	bbs,
>    	     (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
> buc = *(volatile uint8_t *)(rcrb + 0x3414);
> printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled");
> /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
> printf_debug("SPIBAR = 0x%lx\n", tmp + spibar);
> /* TODO: Dump the SPI config regs */
>
> printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, (uint16_t)spibar);
>
> // Assign Virtual Address
> ich_spibar =  rcrb + spibar;
>
> if (ich7_detected) {
> int i;
> printf_debug("0x00: 0x%04x     (SPIS)\n", *(uint16_t *)(ich_spibar + 0));
> printf_debug("0x02: 0x%04x     (SPIC)\n", *(uint16_t *)(ich_spibar + 2));
> printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(ich_spibar + 4));
> for (i=0; i < 8; i++) {
> 	int offs;
> 	offs = 8 + (i * 8);
> 	printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
> 	printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(ich_spibar + offs +4), i);
> }
> printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(ich_spibar + 0x50));
> printf_debug("0x54: 0x%04x     (PREOP)\n", *(uint16_t *)(ich_spibar + 0x54));
> printf_debug("0x56: 0x%04x     (OPTYPE)\n", *(uint16_t *)(ich_spibar + 0x56));
> printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(ich_spibar + 0x58));
> printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(ich_spibar + 0x5c));
> for (i=0; i < 4; i++) {
> 	int offs;
> 	offs = 0x60 + (i * 4);
> 	printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
> }
> printf_debug("\n");
> if ( (*(uint16_t *)ich_spibar) & (1 << 15)) {
> 	printf("WARNING: SPI Configuration Lockdown activated.\n");
> }
>
> }
>
> old = pci_read_byte(dev, 0xdc);
>  printf_debug("SPI Read Configuration: ");
>  new = (old >> 2) & 0x3;
>
> @@ -234,11 +266,16 @@
>    return enable_flash_ich_dc(dev, name);
>  }
>
> +/* Flag for ICH7 SPI register block */
> +int ich7_detected = 0;
>
> static int enable_flash_ich7(struct pci_dev *dev, const char *name)
>  {
>   ich7_detected = 1;
> return enable_flash_ich_dc_spi(dev, name, 0x3020);
>
> }
>
> +/* Flag for ICH8/ICH9 SPI register block */
>  int ich9_detected = 0;
>
> static int enable_flash_ich8(struct pci_dev *dev, const char *name)
> Index: flashrom.c
> ===================================================================
> --- flashrom.c	(revision 3392)
> +++ flashrom.c	(working copy)
> @@ -378,7 +378,7 @@
>  #else
>    if (iopl(3) != 0) {
>  #endif
> fprintf(stderr, "ERROR: iopl failed: \"%s\"\n",
>           fprintf(stderr, "ERROR: Could not get IO privileges (%s).\nYou need to be root.\n",
> strerror(errno));
> exit(1);
>  }
> Index: ichspi.c
>
> --- ichspi.c	(revision 3392)
> +++ ichspi.c	(working copy)
> @@ -4,6 +4,7 @@
> Copyright (C) 2008 Stefan Wildemann
> Copyright (C) 2008 Claus Gindhart
> Copyright (C) 2008 Dominik Geyer
> Copyright (C) 2008 coresystems GmbH
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
>
> @@ -42,15 +43,17 @@
>
> #define MAXDATABYTES 0x40
>
> -/*ICH9 controller register definition*/
> -#define REG_FADDR		0x08	/* 32 Bits */
> -#define REG_FDATA0		0x10	/* 64 Bytes */
> -#define REG_SSFS		0x90	/* 08 Bits */
> +/* ICH9 controller register definition */
> +#define ICH9_REG_FADDR         0x08	/* 32 Bits */
> +#define ICH9_REG_FDATA0                0x10	/* 64 Bytes */
>
> +#define ICH9_REG_SSFS          0x90	/* 08 Bits */
>  #define SSFS_SCIP		0x00000001
>  #define SSFS_CDS		0x00000004
>  #define SSFS_FCERR		0x00000008
>  #define SSFS_AEL		0x00000010
> -#define REG_SSFC		0x91	/* 24 Bits */
>
> +#define ICH9_REG_SSFC          0x91	/* 24 Bits */
>  #define SSFC_SCGO		0x00000200
>  #define SSFC_ACS		0x00000400
>  #define SSFC_SPOP		0x00000800
> @@ -61,16 +64,35 @@
>  #define SSFC_SCF		0x01000000
>  #define SSFC_SCF_20MHZ 0x00000000
>  #define SSFC_SCF_33MHZ 0x01000000
> -#define REG_PREOP		0x94	/* 16 Bits */
> -#define REG_OPTYPE		0x96	/* 16 Bits */
> -#define REG_OPMENU		0x98	/* 64 BITS */
>
> +#define ICH9_REG_PREOP         0x94	/* 16 Bits */
> +#define ICH9_REG_OPTYPE                0x96	/* 16 Bits */
> +#define ICH9_REG_OPMENU                0x98	/* 64 Bits */
>
> // ICH9R SPI commands
>  #define SPI_OPCODE_TYPE_READ_NO_ADDRESS     0
>  #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS    1
>  #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS   2
>  #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS  3
>
> +// ICH7 registers
> +#define ICH7_REG_SPIS          0x00	/* 16 Bits */
> +#define SPIS_SCIP              0x00000001
> +#define SPIS_CDS               0x00000004
> +#define SPIS_FCERR             0x00000008
>
> +#define ICH7_REG_SPIC          0x02	/* 16 Bits */
> +#define SPIC_SCGO              0x0002
> +#define SPIC_ACS               0x0004
> +#define SPIC_SPOP              0x0008
> +#define SPIC_DS                        0x4000
>
> +#define ICH7_REG_SPIA          0x04	/* 32 Bits */
> +#define ICH7_REG_SPID0         0x08	/* 64 Bytes */
> +#define ICH7_REG_PREOP         0x54	/* 16 Bits */
> +#define ICH7_REG_OPTYPE                0x56	/* 16 Bits */
> +#define ICH7_REG_OPMENU                0x58	/* 64 Bits */
>
> typedef struct _OPCODE {
>    uint8_t opcode;		//This commands spi opcode
>    uint8_t spi_type;	//This commands spi type
> @@ -101,10 +123,17 @@
>  static inline uint32_t REGREAD32(int X)
>  {
>    volatile uint32_t regval;
> regval = *(volatile uint32_t *)((uint8_t *) ich_spibar + X);
> regval = *(volatile uint32_t *) ((uint8_t *) ich_spibar + X);
> return regval;
>
> }
>
> +static inline uint16_t REGREAD16(int X)
> +{
> volatile uint16_t regval;
> regval = *(volatile uint16_t *) ((uint8_t *) ich_spibar + X);
> return regval;
>
> +}
>
> #define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)ich_spibar+X)=Y)
>  #define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)ich_spibar+X)=Y)
>  #define REGWRITE8(X,Y)  (*(uint8_t *)((uint8_t *)ich_spibar+X)=Y)
> @@ -114,9 +143,9 @@
>  static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
>    	      uint8_t datalength, uint8_t * data);
>  static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
> 	     int Offset);
> 	     int offset);
>
> static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
> 	      int Offset);
> 	      int offset);
>
> static int ich_spi_erase_block(struct flashchip *flash, int offset);
>
> OPCODES O_ST_M25P = {
> @@ -147,37 +176,61 @@
>    temp16 = (op->preop[0]);
>    /* 8:16 Prefix Opcode 2 */
>    temp16 |= ((uint16_t) op->preop[1]) << 8;
> REGWRITE16(REG_PREOP, temp16);
> if (ich7_detected) {
> REGWRITE16(ICH7_REG_PREOP, temp16);
> } else if (ich9_detected) {
> REGWRITE16(ICH9_REG_PREOP, temp16);
> }
> /*Program Opcode Types 0 - 7 */
> /* Program Opcode Types 0 - 7 */
> temp16 = 0;
> for (a = 0; a < 8; a++) {
> temp16 |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
> }
>
> REGWRITE16(REG_OPTYPE, temp16);
>
> /*Program Allowable Opcodes 0 - 3 */
> if (ich7_detected) {
> REGWRITE16(ICH7_REG_OPTYPE, temp16);
> } else if (ich9_detected) {
> REGWRITE16(ICH9_REG_OPTYPE, temp16);
> }
> /* Program Allowable Opcodes 0 - 3 */
> temp32 = 0;
> for (a = 0; a < 4; a++) {
> temp32 |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
> }
> REGWRITE32(REG_OPMENU, temp32);
> if (ich7_detected) {
> REGWRITE32(ICH7_REG_OPMENU, temp32);
> } else if (ich9_detected) {
> REGWRITE32(ICH9_REG_OPMENU, temp32);
> }
> /*Program Allowable Opcodes 4 - 7 */
>  temp32 = 0;
>  for (a = 4; a < 8; a++) {
> temp32 |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
> temp32 |=
>     ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
> }
> REGWRITE32(REG_OPMENU + 4, temp32);
> if (ich7_detected) {
> REGWRITE32(ICH7_REG_OPMENU + 4, temp32);
> } else if (ich9_detected) {
> REGWRITE32(ICH9_REG_OPMENU + 4, temp32);
> }
> return 0;
>
> }
>
> -int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength,
>       uint8_t * data)
>
> +static int ich7_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
> 	   uint8_t datalength, uint8_t * data)
>
> {
>    int write_cmd = 0;
>
> int timeout;
> uint32_t temp32;
>
> uint16_t temp16;
> uint32_t a;
>
> /* Is it a write command? */
>
> @@ -187,7 +240,7 @@
>    }
>
> /* Programm Offset in Flash into FADDR */
> REGWRITE32(REG_FADDR, (offset & 0x00FFFFFF));	/*SPI addresses are 24 BIT only */
>
> REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF));	/* SPI addresses are 24 BIT only */
>
> /* Program data into FDATA0 to N */
> if (write_cmd && (datalength != 0)) {
>
> @@ -200,16 +253,119 @@
>    		temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
> 	if ((a % 4) == 3) {
> 		REGWRITE32(REG_FDATA0 + (a - (a % 4)), temp32);
> 		REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
> 			   temp32);
> }
> }
> if (((a - 1) % 4) != 3) {
> 	REGWRITE32(REG_FDATA0 + ((a - 1) - ((a - 1) % 4)),
> 		   temp32);
> 	REGWRITE32(ICH7_REG_SPID0 +
> 		   ((a - 1) - ((a - 1) % 4)), temp32);
>
> }
>
> }
>
> /* Assemble SPIS */
>
> temp16 = 0;
>
> /* clear error status registers */
>
> temp16 |= (SPIS_CDS + SPIS_FCERR);
>
> REGWRITE16(ICH7_REG_SPIS, temp16);
>
> /* Assemble SPIC */
>
> temp16 = 0;
>
> if (datalength != 0) {
> temp16 |= SPIC_DS;
> temp16 |= ((uint16_t) ((datalength - 1) & 0x3f)) << 8;
>
> }
>
> /* Select opcode */
>
> temp16 |= ((uint16_t) (nr & 0x07)) << 4;
>
> /* Handle Atomic */
>
> if (op.atomic != 0) {
> /* Select atomic command */
> temp16 |= SPIC_ACS;
> /* Selct prefix opcode */
> if ((op.atomic - 1) == 1) {
> 	/*Select prefix opcode 2 */
> 	temp16 |= SPIC_SPOP;
> }
>
> }
>
> /* Start */
>
> temp16 |= SPIC_SCGO;
>
> /* write it */
>
> REGWRITE16(ICH7_REG_SPIC, temp16);
>
> /* wait for cycle complete */
>
> timeout = 1000 * 60;	// 60s is a looong timeout.
>
> while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
> myusec_delay(1000);
>
> }
>
> if (!timeout) {
> printf_debug("timeout\n");
>
> }
>
> if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
> printf_debug("Transaction error!\n");
> return 1;
>
> }
>
> if ((!write_cmd) && (datalength != 0)) {
> for (a = 0; a < datalength; a++) {
> 	if ((a % 4) == 0) {
> 		temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
> 	}
> 	data[a] =
> 	    (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
> 	    >> ((a % 4) * 8);
> }
>
> }
>
> return 0;
>
> +}
>
> +static int ich9_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
> 	   uint8_t datalength, uint8_t * data)
>
> +{
> int write_cmd = 0;
> uint32_t temp32;
> uint32_t a;
> /* Is it a write command? */
> if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
>    || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
> write_cmd = 1;
> }
> /* Programm Offset in Flash into FADDR */
> REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF));	/* SPI addresses are 24 BIT only */
> /* Program data into FDATA0 to N */
> if (write_cmd && (datalength != 0)) {
> temp32 = 0;
> for (a = 0; a < datalength; a++) {
> 	if ((a % 4) == 0) {
> 		temp32 = 0;
> 	}
> 	temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
> 	if ((a % 4) == 3) {
> 		REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
> 			   temp32);
> 	}
> }
> if (((a - 1) % 4) != 3) {
> 	REGWRITE32(ICH9_REG_FDATA0 +
> 		   ((a - 1) - ((a - 1) % 4)), temp32);
> }
> }
> /* Assemble SSFS + SSFC */
>  temp32 = 0;
>
> @@ -243,15 +399,15 @@
>    temp32 |= SSFC_SCGO;
>
> /* write it */
> REGWRITE32(REG_SSFS, temp32);
>
> REGWRITE32(ICH9_REG_SSFS, temp32);
>
> /*wait for cycle complete */
> while ((REGREAD32(REG_SSFS) & SSFS_CDS) == 0) {
> while ((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) {
> /*TODO; Do something that this can't lead into an endless loop. but some
> commands may cause this to be last more than 30 seconds */
> }
> if ((REGREAD32(REG_SSFS) & SSFS_FCERR) != 0) {
> if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
> printf_debug("Transaction error!\n");
> return 1;
> }
>
> @@ -259,21 +415,35 @@
>    if ((!write_cmd) && (datalength != 0)) {
>    	for (a = 0; a < datalength; a++) {
>    		if ((a % 4) == 0) {
> 		temp32 = REGREAD32(REG_FDATA0 + (a));
> 		temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
> }
>
> data[a] =
> 	    (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) >>
> 	    ((a % 4) * 8);
> 	    (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
> 	    >> ((a % 4) * 8);
>
> }
> }
>
> return 0;
>
> }
>
> +static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
>       uint8_t datalength, uint8_t * data)
>
> +{
> if (ich7_detected)
> return ich7_run_opcode(nr, op, offset, datalength, data);
> else if (ich9_detected) {
> return ich9_run_opcode(nr, op, offset, datalength, data);
> }
> /* If we ever get here, something really weird happened */
> return -1;
>
> +}
>
> static int ich_spi_erase_block(struct flashchip *flash, int offset)
>  {
> printf_debug("Spi_Erase,Offset=%d,sectors=%d\n", offset, 1);
>
> printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n",
>      offset, 1);
>
> if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) {
> printf_debug("Error erasing sector at 0x%x", offset);
>
> @@ -285,21 +455,21 @@
>    return 0;
>  }
>
> -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int Offset)
> +static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset)
>  {
>    int page_size = flash->page_size;
>    uint32_t remaining = flash->page_size;
>    int a;
> printf_debug("Spi_Read,Offset=%d,number=%d,buf=%p\n", Offset, page_size,
>      buf);
>
> printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n",
>      offset, page_size, buf);
>
> for (a = 0; a < page_size; a += MAXDATABYTES) {
> if (remaining < MAXDATABYTES) {
> if (run_opcode
>     (1, curopcodes->opcode[1],
> 	     Offset + (page_size - remaining), remaining,
> 	     offset + (page_size - remaining), remaining,
>      &buf[page_size - remaining]) != 0) {
> 	printf_debug("Error reading");
> 	return 1;
>
> @@ -308,7 +478,7 @@
>    	} else {
>    		if (run_opcode
>    		    (1, curopcodes->opcode[1],
> 	     Offset + (page_size - remaining), MAXDATABYTES,
> 	     offset + (page_size - remaining), MAXDATABYTES,
>      &buf[page_size - remaining]) != 0) {
> 	printf_debug("Error reading");
> 	return 1;
>
> @@ -321,20 +491,20 @@
>  }
>
> static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
> 	      int Offset)
> 	      int offset)
>
> {
>    int page_size = flash->page_size;
>    uint32_t remaining = page_size;
>    int a;
> printf_debug("write_page_ichspi,Offset=%d,number=%d,buf=%p\n", Offset,
>      page_size, bytes);
>
> printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
>      offset, page_size, bytes);
>
> for (a = 0; a < page_size; a += MAXDATABYTES) {
> if (remaining < MAXDATABYTES) {
> 	if (run_opcode
> 	    (0, curopcodes->opcode[0],
> 	     Offset + (page_size - remaining), remaining,
> 	     offset + (page_size - remaining), remaining,
>      &bytes[page_size - remaining]) != 0) {
> 	printf_debug("Error writing");
> 	return 1;
>
> @@ -343,7 +513,7 @@
>    	} else {
>    		if (run_opcode
>    		    (0, curopcodes->opcode[0],
> 	     Offset + (page_size - remaining), MAXDATABYTES,
> 	     offset + (page_size - remaining), MAXDATABYTES,
>      &bytes[page_size - remaining]) != 0) {
> 	printf_debug("Error writing");
> 	return 1;