Yes, but you'd better to use southbridge/amd/cimx/sb800/, please reference mainboard/advansus/a785e-i.
Thanks, I was trying that, mach less success here:
coreboot-4.0-2540-g246e84b-dirty Mon Jul 16 21:17:05 MSK 2012 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1041, current patch id = 0x00000000 microcode: rev id (1043) does not match this patch. microcode: Not updated! Fix microcode_updates[] POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB800 - src/southbridge/amd/cimx/sb800/early.c - get_sbdn - Start. SB800 - src/southbridge/amd/cimx/sb800/early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f24 F3xD8: 03001816 F3xDC: 00006322 POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 POST: 0x37 started ap apicid: * AP 01 timed out:00000001 * AP 02 timed out:00000001 * AP 03 timed out:00000001
POST: 0x38 rs780_early_setup() fam10_optimization() rs780_por_init
Begin FIDVID MSR 0xc0010071 0x30b800a3 0x40035840 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 10600 Wait for AP stage 1: ap_apicid = 1 init_fidvid_bsp_stage1: timed out reading from ap 01 Wait for AP stage 1: ap_apicid = 2 init_fidvid_bsp_stage1: timed out reading from ap 02 Wait for AP stage 1: ap_apicid = 3 init_fidvid_bsp_stage1: timed out reading from ap 03 common_fid = 10600 FID Change Node:00, F3xD4: c8810f26 POST: 0x3a End FIDVIDMSR 0xc0010071 0x30b800a3 0x38005840 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode ...WARM RESET...