the following patch was just integrated into master: commit da3087f67d516350249779745927861c4da2173d Author: Marc Jones marc.jones@se-eng.com Date: Mon Nov 5 17:25:52 2012 -0700
Mainboard SMI S state handler was using the wrong defines
The PCH register bit definition for sleep type is a little confusing. For example, 7 is S5. To make this simpler for the mainbaord developer, the mainboard smi sleep hander is called as mainboard_sleep(slp_typ-2). A couple mainboard SMI handlers were using the PCH define for slp_ty, so S3 code would be run for S5 and S5 code would never be run.
Change-Id: Iaecf96bfd48cf00153600cd119760364fbdfc29e Signed-off-by: Marc Jones marc.jones@se-eng.com Reviewed-on: http://review.coreboot.org/2514 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Ronald G. Minnich rminnich@gmail.com
Build-Tested: build bot (Jenkins) at Tue Feb 26 01:40:15 2013, giving +1 Reviewed-By: Ronald G. Minnich rminnich@gmail.com at Wed Feb 27 03:03:05 2013, giving +2 See http://review.coreboot.org/2514 for details.
-gerrit