I also start to be confused.
In the sb700 rrg, it says the default value of reg [0x14,3,0x6c] is 0xFFF8, which means 512K. But actually, I took a look at the real board with a blank BIOS chip. The default value is 0xFFF0, which means 1MB.
I think we should believe the real thing other than the datasheet when they conflict.
Zheng
-----Original Message----- From: Uwe Hermann [mailto:uwe@hermann-uwe.de] Sent: Tuesday, December 14, 2010 10:05 AM To: Bao, Zheng Cc: Stefan Reinauer; Scott Duplichan; Peter Stuge;
coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE (Patch is updated)
Hi,
On Mon, Dec 13, 2010 at 05:47:33PM +0800, Bao, Zheng wrote:
+config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/sb600/bootblock.c"
- depends on SOUTHBRIDGE_AMD_SB600
[...]
+config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/sb700/bootblock.c"
- depends on SOUTHBRIDGE_AMD_SB700
Thanks for adding these, looks like I forgot them in the
TINY_BOOTBLOCK
patches.
- Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF.
- Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
- Hardware should enable LPC ROM by pin straps. This function does
not
- handle the theoretically possible PCI ROM, FWH, or SPI ROM
configurations.
- The SB700 power-on default is to map 256K ROM space.
- The SB700 power-on default is to map 512K ROM space.
Nice! I guess these new values are correct, however I could not find this specified in the SB700 datasheets (?) Is this undocumented or did I not look in the right place?
The BKDG at
http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf
says:
"Upon system power on, the SB700 enables 256K ROM by default. The BIOS needs to enable 512K ROM or up to 1M for LPC ROM, if required."
It also only mentions 512KB and 1MB configs (no mention of up to 4MB being supported). Is the datasheet outdated maybe?
Thanks, Uwe.
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