On Thu, 8 May 2003, Nathanael Noblet wrote:
So I have the datasheet for the 5595 now (found using google so not sure whether I should send it to you) um either way to enable flash they talk about using the
send me the URL.
"Register 70h to register 76h define the attribute of the Shadow RAM from 640 KBytes to 1 MBytes. All of the registers 70h to 75h are defined as below, and each register defines the corresponding memory segment's attribute which are listed in the following table. REGISTER DEFINED RANGE REGISTER DEFINED RANGE Register 70h bits 7:5 0C0000h-0C3FFFh Register 73h bits 7:5 0D8000h-0DBFFFh"
not needed.
Register 45h (on the 5595) controls the flash writability. But on the sis530 45h is "IDE Secondary Channel/Master Drive Data Active Time Control" so again it is a matter of knowing how to communicate with the 5595 instead of the main chipset.
I think I need to see the doc.
Now this is all great and what not, but I'm confused. We're having problems detecting the flash, not writing to it. So I'm not sure how this will help. As well in the flash_rom sources the enable_sis is never called.
the reason is that you can't ID a flash without having write access to it.
- Does the write enable bit help with detecting?
it is essential. Must have it.
- Where do I get docs about how the pci & isa communication happens? 2a) do I need those docs?
send me the URL first. If it's legal to look at the doc I will take a look.
ron