Author: mraudsepp Date: 2008-11-06 18:52:52 +0100 (Thu, 06 Nov 2008) New Revision: 985
Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/dts Log: cs5536: Support NAND flash on other locations than CS0
Modify chipset_flash_setup to support enabling NAND flash on other locations than CS0, by making enable_ide_nand_flash have a non-boolean meaning where zero means no NAND (IDE), and 1 through 4 gives the one-based chip select array location (so 1 means CS0, 2 means CS1, 3 means CS2 and 4 means CS3, as chip select notation is zero-based).
This loses the code for supporting more than one NAND chip select or different ones than FLASH_MEM_4K, but these couldn't be supported before anyway, because that is board specific, but the supporting structure was a static const struct in generic southbridge specific code. This support should be instead implemented via the device tree dts files.
Enables NAND on ArtecGroup DBE61 and DBE62 on CS1, as that's where it is. The end result is that these mainboards can now boot off of NAND with FILO without local modifications to the previously existing southbridge specific static const struct that had no chance of being upstreamed as it would break all other CS5536 NAND boards that have it on CS0.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-11-06 13:59:14 UTC (rev 984) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-11-06 17:52:52 UTC (rev 985) @@ -44,8 +44,8 @@ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; - /* 0:IDE 1:FLASH */ - enable_ide_nand_flash = "1"; + /* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */ + enable_ide_nand_flash = "2"; /* we use com2 since that is on the dongle */ com2_enable = "1"; /* Set com2 address to be COM1 */
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-11-06 13:59:14 UTC (rev 984) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-11-06 17:52:52 UTC (rev 985) @@ -68,19 +68,6 @@ {0, 0} };
-struct FLASH_DEVICE { - unsigned char fType; /* Flash type: NOR or NAND */ - unsigned char fInterface; /* Flash interface: I/O or memory */ - unsigned long fMask; /* Flash size/mask */ -}; - -static const struct FLASH_DEVICE FlashInitTable[] = { - {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */ -}; - static const u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, @@ -154,38 +141,31 @@ * correct size info. Call this routine only if flash needs to be * configured (don't call it if you want IDE). */ -static void chipset_flash_setup(void) +static void chipset_flash_setup(struct southbridge_amd_cs5536_dts_config *sb) { int i; struct msr msr;
printk(BIOS_DEBUG, "chipset_flash_setup: Start\n"); - for (i = 0; i < ARRAY_SIZE(FlashInitTable); i++) { - if (FlashInitTable[i].fType != FLASH_TYPE_NONE) { - printk(BIOS_DEBUG, "Enable CS%d\n", i); - /* We need to configure the memory/IO mask. */ - msr = rdmsr(FlashPort[i]); - msr.hi = 0; /* Start with "enabled" bit clear. */ - if (FlashInitTable[i].fType == FLASH_TYPE_NAND) - msr.hi |= 0x00000002; - else - msr.hi &= ~0x00000002; - if (FlashInitTable[i].fInterface == FLASH_IF_MEM) - msr.hi |= 0x00000004; - else - msr.hi &= ~0x00000004; - msr.hi |= FlashInitTable[i].fMask; - printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", - FlashPort[i], msr.hi, msr.lo); - wrmsr(FlashPort[i], msr); + if (sb->enable_ide_nand_flash <= 4) { + i = sb->enable_ide_nand_flash - 1; + printk(BIOS_DEBUG, "Enable CS%d\n", i); + /* We need to configure the memory/IO mask. */ + msr = rdmsr(FlashPort[i]); + msr.hi = 0; /* Start with "enabled" bit clear. */ + msr.hi |= 0x00000002; /* For FLASH_TYPE_NAND */ + msr.hi |= 0x00000004; /* For FLASH_IF_MEM */ + msr.hi |= FLASH_MEM_4K; + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", + FlashPort[i], msr.hi, msr.lo); + wrmsr(FlashPort[i], msr);
- /* Now write-enable the device. */ - msr = rdmsr(MDD_NORF_CNTRL); - msr.lo |= (1 << i); - printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", - MDD_NORF_CNTRL, msr.hi, msr.lo); - wrmsr(MDD_NORF_CNTRL, msr); - } + /* Now write-enable the device. */ + msr = rdmsr(MDD_NORF_CNTRL); + msr.lo |= (1 << i); + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", + MDD_NORF_CNTRL, msr.hi, msr.lo); + wrmsr(MDD_NORF_CNTRL, msr); } printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n"); } @@ -596,9 +576,9 @@
/* Flash BAR size setup. */ printk(BIOS_ERR, "%sDoing chipset_flash_setup()\n", - sb->enable_ide_nand_flash == 1 ? "" : "Not "); - if (sb->enable_ide_nand_flash == 1) - chipset_flash_setup(); + sb->enable_ide_nand_flash != 0 ? "" : "Not "); + if (sb->enable_ide_nand_flash != 0) + chipset_flash_setup(sb);
/* Set up hardware clock gating. */ /* TODO: Why the extra block here? Can it be removed? */ @@ -680,7 +660,7 @@
printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash); - if (sb->enable_ide_nand_flash == 1) + if (sb->enable_ide_nand_flash != 0) enable_ide_nand_flash_header();
enable_USB_port4(sb);
Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-11-06 13:59:14 UTC (rev 984) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-11-06 17:52:52 UTC (rev 985) @@ -33,7 +33,7 @@ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */ enable_gpio_int_route = "0";
- /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */ + /* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */ enable_ide_nand_flash = "0";
/* Enable USB Port 4 (0:host 1:device).