[coreboot] r3148 - in trunk/coreboot-v2/src: mainboard/asus/a8v-e_se southbridge/via/vt8237r

Author: ruik
Date: 2008-03-15 01:26:50 +0100 (Sat, 15 Mar 2008)
New Revision: 3148

Modified:
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
Log:
Following patch extends the ROM decoding to last 1MB, allowing to use larger
flashes such as SST49LF080A: 1024K x8 (8 Mbit)

Tested on my system, the flash is found and if I use coreboot in second half it
works too.

Signed-off-by: Rudolf Marek 
Acked-by: Carl-Daniel Hailfinger

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	2008-03-15 00:19:34 UTC (rev 3147)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	2008-03-15 00:26:50 UTC (rev 3148)
@@ -192,6 +192,7 @@
    w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
    uart_init();
    console_init();
+	enable_rom_decode();

print_info("now booting... fallback\r\n");

@@ -259,6 +260,7 @@
    w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
    uart_init();
    console_init();
+	enable_rom_decode();

print_info("now booting... real_main\r\n");

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2008-03-15 00:19:34 UTC (rev 3147)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2008-03-15 00:26:50 UTC (rev 3148)
@@ -212,3 +212,18 @@
    else
    	PRINT_DEBUG("Done\r\n");
 }
+
+void enable_rom_decode(void)
+{
+	device_t dev;
+
+	/* Bus Control and Power Management  */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+
+	if (dev == PCI_DEV_INVALID)
+		die("SB not found\r\n");
+
+	/* ROM decode last 1MB FFC00000 - FFFFFFFF */
+	pci_write_config8(dev, 0x41, 0x7f);
+}