On Thu, Mar 5, 2009 at 2:22 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 05.03.2009 21:57, Marc Jones wrote:
Add K8 support for some of the more important MSRs.
Signed-off-by: Marc Jones marcj303@gmail.com
If you fix the one bug mentioned below and can provide explanations/answers for my other questions, this is Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
- { 0xC001001A, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM Register", "This register indicates the first byte of I/O above DRAM", {
- { 63, 24, RESERVED },
- { 39, 8, "TOM 16-9", "", PRESENT_HEX, {
I find the bit numbering in the description string here to be rather unintuitive. IIRC these bits here are not shifted, so "TOM 29-32" would be the correct name.
Ok, changed.
Can TOP_MEM really be larger than 4 GB?
I have never seen it but it seems so from the BKDG. You wouldn't be able to hoist them memory in the MMIO hole if you did it this way.
I thought newer AMD processors have more than 40 bit addressable memory.
Fam10 does.
- { 0xC0010019, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask0", "This register holds the mask of the variable I/O range", {
Should be IORRMask1.
Fixed.
-const uint32_t msraddrbyname(const char *name) { +uint32_t msraddrbyname(const char *name) {
Any reason for the const removal? The changelog doesn't say anything about it.
That was to get it to compile with -Werror which is on by default. It didn't look like that really needed to be a const.
Marc