15 May
2007
15 May
'07
12:28 a.m.
I've taken notes on the following aspects of the Northbridge and am reading the Intel published SPD pdf now.
The following is only some clippings of what is said in the main pdf and the updates concerning DRAM config. I think I have yet to go through each DRAM register looking for notes pertaining to "what should be set before/after SPD".
-- Roger http://www.eskimo.com/~roger/index.html Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Mon May 14 17:23:51 PDT 2007