Frank Vibrans III (efdesign98@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/97
-gerrit
commit deaac0427cf5023064fb2975d1efcb1e934b1208 Author: efdesign98 efdesign98@gmail.com Date: Wed Jul 13 17:16:13 2011 -0700
Add AMD Family 10 support to cpu folder
This change adds the AMD Family 10 cpu support to the cpu folder. It also updates the makefiles of the Families 12 and 14 to take advantage of a pair of shared files that are moved to the cpu/agesa folder.
Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2 Signed-off-by: Frank Vibrans frank.vibrans@amd.com Signed-off-by: efdesign98 efdesign98@gmail.com --- src/cpu/amd/Makefile.inc | 1 - src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/agesa/Makefile.inc | 4 + src/cpu/amd/agesa/apic_timer.c | 59 +++++ src/cpu/amd/agesa/cache_as_ram.inc | 97 +++++++++ src/cpu/amd/agesa/family10/Kconfig | 64 ++++++ src/cpu/amd/agesa/family10/Makefile.inc | 304 +++++++++++++++++++++++++++ src/cpu/amd/agesa/family10/chip.h | 23 ++ src/cpu/amd/agesa/family10/chip_name.c | 25 +++ src/cpu/amd/agesa/family10/model_10_init.c | 133 ++++++++++++ src/cpu/amd/agesa/family12/Makefile.inc | 4 - src/cpu/amd/agesa/family12/apic_timer.c | 58 ----- src/cpu/amd/agesa/family12/cache_as_ram.inc | 98 --------- src/cpu/amd/agesa/family14/Makefile.inc | 2 - src/cpu/amd/agesa/family14/apic_timer.c | 58 ----- src/cpu/amd/agesa/family14/cache_as_ram.inc | 98 --------- 16 files changed, 710 insertions(+), 319 deletions(-)
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index c29b730..e695473 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -15,4 +15,3 @@ subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
subdirs-$(CONFIG_AMD_AGESA) += agesa -subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa/f14 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 1aa9544..60bb74b 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -17,5 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
+source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index d0538b8..4331435 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -16,5 +16,9 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 + +ramstage-y += apic_timer.c +cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/apic_timer.c b/src/cpu/amd/agesa/apic_timer.c new file mode 100755 index 0000000..ec6ddd5 --- /dev/null +++ b/src/cpu/amd/agesa/apic_timer.c @@ -0,0 +1,59 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include <stdint.h> +#include <delay.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> + +/* NOTE: We use the APIC TIMER register is to hold flags for AP init during + * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is + * redirected to udelay_tsc(). + */ + + +void init_timer(void) +{ + /* Set the apic timer to no interrupts and periodic mode */ + lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); + + /* Set the divider to 1, no divider */ + lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); + + /* Set the initial counter to 0xffffffff */ + lapic_write(LAPIC_TMICT, 0xffffffff); + +} + + +void udelay(u32 usecs) +{ + u32 start, value, ticks; + /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ + ticks = usecs * 200; + start = lapic_read(LAPIC_TMCCT); + do { + value = lapic_read(LAPIC_TMCCT); + } while((start - value) < ticks); + +} diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc new file mode 100755 index 0000000..f328db4 --- /dev/null +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/****************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * $Workfile:: cache_as_ram.inc + * + * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier + * + ****************************************************************************** + */ + +#include "gcccar.inc" + +/* + * XMM map: + * xmm0: BIST + * xmm1: backup ebx -- cpu_init_detected + */ + +.code32 +.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out + +cache_as_ram_setup: + + post_code(0xa0) + + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + + movl %cr4, %eax + orl $(3<<9), %eax + movl %eax, %cr4 + + /* Get the cpu_init_detected */ + mov $1, %eax + cpuid + shr $24, %ebx + + /* Save the BIST result */ + cvtsi2sd %ebp, %xmm0 + + /* for normal part %ebx already contain cpu_init_detected from fallback call */ + + /* Save the cpu_init_detected */ + cvtsi2sd %ebx, %xmm1 + + post_code(0xa1) + AMD_ENABLE_STACK + + post_code(0xa1) + + /* Restore the BIST result */ + cvtsd2si %xmm0, %edx + + /* Restore the cpu_init_detected */ + cvtsd2si %xmm1, %ebx + + pushl %ebx /* init detected */ + pushl %edx /* bist */ + call cache_as_ram_main + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop + +disable_cache_as_ram: + /* Save return stack */ + movd %esp, %xmm0 + + AMD_DISABLE_STACK + + /* Restore the return stack */ + movd %xmm0, %esp + ret + +cache_as_ram_setup_out: + + diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig new file mode 100755 index 0000000..81070e5 --- /dev/null +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -0,0 +1,64 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY10 + bool + select CPU_AMD_MODEL_10XXX + select PCI_IO_CFG_EXT + +if CPU_AMD_AGESA_FAMILY10 + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x80000 + +config HAVE_INIT_TIMER + bool + default y + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + depends on CPU_AMD_AGESA_FAMILY10 + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD AGESA code. + +endif #CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family10/Makefile.inc b/src/cpu/amd/agesa/family10/Makefile.inc new file mode 100755 index 0000000..6981a47 --- /dev/null +++ b/src/cpu/amd/agesa/family10/Makefile.inc @@ -0,0 +1,304 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += chip_name.c +driver-y += model_10_init.c + +AGESA_ROOT = ../../../../vendorcode/amd/agesa/f10 + +#agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/F10IoCstate.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c + +agesa_lib_src = $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/mrdef.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10PowerPlane.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Perf/IdsPerf.c +agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsCtrl.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c + +#agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/ON/mrnmcton.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/OR/mrnprotoor.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/mrm.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/mruc.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/CPU/cpuRecovery.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitRecovery.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/mrntrain3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrt3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/mrn.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/mrttpos.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/mrnmct.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/mrndct.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/mrttsrc.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnS3on.c +#agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/OLSPARE/mfspr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuMsgBasedC1e.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/NbCommon/htNbCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/NbCommon/htNbNonCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/NbCommon/htNbOptimization.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/NbCommon/htNbUtilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbCoherentFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbOptimizationFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbNonCoherentFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbUtilitiesFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbSystemFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatDynamicDiscovery.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatSets.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatGanging.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatSublinks.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatNoncoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatTrafficDistribution.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatOptimization.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htIds.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatRouting.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10PciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10PowerCheck.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandId.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10Dmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10Pstate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10Utilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10MsrTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10EarlyInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c + +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph1.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6DoubloonUpper.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph2.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph3Line.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6TwinTriangles.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph3Triangle.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6TwistedLadder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Degenerate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph7FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph7TwistedLadder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Kite.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8DoubloonM.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Line.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Square.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8Ladder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Star.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph5FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8TwistedLadder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph5TwistedLadder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6DoubloonLower.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/HY/mmflowhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/NDINTLV/mfndi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnS3hy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mndcthy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnflowhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnidendimmhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnmcthy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnothy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnParTrainHy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnphyhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnprotohy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnreghy.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/HY/mprhy3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/HY/mpuhy3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/HY/mpshy3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/HY/marhy3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/HY/mauhy3.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtAssist.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/F10PmNbPstateInit.c + +##C32 +#agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/C32/mmflowC32.c + +romstage-y += $(agesa_lib_src) +ramstage-y += $(agesa_lib_src) + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm + diff --git a/src/cpu/amd/agesa/family10/chip.h b/src/cpu/amd/agesa/family10/chip.h new file mode 100755 index 0000000..d5a749b --- /dev/null +++ b/src/cpu/amd/agesa/family10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_agesa_family10_ops; + +struct cpu_amd_agesa_family10_config { +}; diff --git a/src/cpu/amd/agesa/family10/chip_name.c b/src/cpu/amd/agesa/family10/chip_name.c new file mode 100755 index 0000000..d99769c --- /dev/null +++ b/src/cpu/amd/agesa/family10/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_amd_agesa_family10_ops = { + CHIP_NAME("AMD CPU Family 10h") +}; diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c new file mode 100755 index 0000000..8c1cfad --- /dev/null +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> + +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include "northbridge/amd/agesa/family10/amdfam10.h" + +#define MCI_STATUS 0x401 + +static msr_t rdmsr_amd(u32 index) +{ + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static void wrmsr_amd(u32 index, msr_t msr) +{ + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); +} + +static void model_10_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); + + u8 i; + msr_t msr; +#if CONFIG_LOGICAL_CPUS == 1 + u32 siblings; +#endif + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + amd_setup_mtrrs(); + x86_mtrr_check(); + + disable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + enable_cache(); + + /* Enable the local cpu apics */ + setup_lapic(); + + /* Set the processor name string */ + // init_processor_name(); + + +#if CONFIG_LOGICAL_CPUS == 1 + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_10_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { 0, 0 }, +}; + +static const struct cpu_driver model_10 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 4e69355..5aa4127 100755 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -320,7 +320,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm - -ramstage-y += apic_timer.c - -cpu_incs += $(src)/cpu/amd/agesa/family12/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family12/apic_timer.c b/src/cpu/amd/agesa/family12/apic_timer.c deleted file mode 100755 index 26d3f88..0000000 --- a/src/cpu/amd/agesa/family12/apic_timer.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/amd/agesa/family12/cache_as_ram.inc b/src/cpu/amd/agesa/family12/cache_as_ram.inc deleted file mode 100755 index 98da3cb..0000000 --- a/src/cpu/amd/agesa/family12/cache_as_ram.inc +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/****************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * $Workfile:: cache_as_ram.inc - * - * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier - * - ****************************************************************************** - */ - -#include "gcccar.inc" - -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - -.code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out - -cache_as_ram_setup: - - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ - - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 - - post_code(0xa1) - AMD_ENABLE_STACK - - post_code(0xa1) - - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx - - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx - - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main - - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop - -disable_cache_as_ram: - /* Save return stack */ - cvtsi2sd %esp, %xmm0 - - AMD_DISABLE_STACK - - /* Restore the return stack */ - cvtsd2si %xmm0, %esp - - ret - -cache_as_ram_setup_out: - - diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 1e0f37b..3039300 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -278,5 +278,3 @@ subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm
-ramstage-y += apic_timer.c -cpu_incs += $(src)/cpu/amd/agesa/family14/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family14/apic_timer.c b/src/cpu/amd/agesa/family14/apic_timer.c deleted file mode 100644 index 26d3f88..0000000 --- a/src/cpu/amd/agesa/family14/apic_timer.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/amd/agesa/family14/cache_as_ram.inc b/src/cpu/amd/agesa/family14/cache_as_ram.inc deleted file mode 100644 index 98da3cb..0000000 --- a/src/cpu/amd/agesa/family14/cache_as_ram.inc +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/****************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * $Workfile:: cache_as_ram.inc - * - * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier - * - ****************************************************************************** - */ - -#include "gcccar.inc" - -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - -.code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out - -cache_as_ram_setup: - - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ - - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 - - post_code(0xa1) - AMD_ENABLE_STACK - - post_code(0xa1) - - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx - - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx - - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main - - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop - -disable_cache_as_ram: - /* Save return stack */ - cvtsi2sd %esp, %xmm0 - - AMD_DISABLE_STACK - - /* Restore the return stack */ - cvtsd2si %xmm0, %esp - - ret - -cache_as_ram_setup_out: - -