Thank you very much! Perhaps I'm going to expand HAVE_ACPI_RESUME option for G505S like " Select this to make S3 resume working or disable it for increased security. Enables CBMEM_STAGE_CACHE and disables SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT."
On Sun, Nov 3, 2019 at 5:23 PM Kyösti Mälkki kyosti.malkki@gmail.com wrote:
On Sun, Nov 3, 2019 at 3:48 PM Mike Banon mikebdp2@gmail.com wrote:
Good day! Starting with commit 0a4457ff44b10f22b711f64e88888c757fbedf32 which introduced a disabled-by-default CONFIG_CBMEM_STAGE_CACHE option - https://github.com/coreboot/coreboot/commit/0a4457ff44b10f22b711f64e88888c75...
- S3 resume freezes on G505S if this option isn't enabled.
Commit message tells that "AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option.", however I've waited for like an hour but it's still stuck and can't be turned on later without a force shutdown and full laptop discharge.
Well.. it would not be first or the last time when I write commit messages anticipating certain things to happen, while not having fully tested all aspects.
There's the same behavior for a fresh coreboot as well. Here is my coreboot config I've used as a base - https://pastebin.com/6Nj6e6xZ . Is this problem expected? If not, I could help by testing your debug builds aimed on fixing it.
Just add 'select CBMEM_STAGE_CACHE' for fam14, fam15tn and fam16kb for now. I kind of came across this problem recently but did not make any debugging attempts yet.
In addition, S3 resume is also not working with CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT even if CONFIG_CBMEM_STAGE_CACHE is enabled.
We did discuss this before in gerrit, I could not find the link though. AGESA has some valuables at around 128 MiB (or was it 64 MiB) in ramstage that coreboot proper does not really know about. Clearing that wipes out cached RAM training data before it is written to SPI flash.
Kyösti