Ricardo Martins (rasmartins@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1152
-gerrit
commit 4c8a557d3ea3728773e1d9dcd59edb22436199ec Author: Ricardo Martins rasmartins@gmail.com Date: Fri Jul 6 13:44:41 2012 +0100
IEI PM-LX2-800-R10: Added preliminary mainboard support
Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=000010000...
Most of the functionality provided by the original BIOS is implemented.
Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins rasmartins@gmail.com --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx2-800-r10/Kconfig | 71 +++++++++++++ src/mainboard/iei/pm-lx2-800-r10/chip.h | 23 ++++ src/mainboard/iei/pm-lx2-800-r10/cmos.layout | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/devicetree.cb | 87 +++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/irq_tables.c | 134 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/it8888_io.def | 27 +++++ src/mainboard/iei/pm-lx2-800-r10/mainboard.c | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/romstage.c | 101 ++++++++++++++++++ 9 files changed, 652 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index ea26922..537252d 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -31,6 +31,8 @@ config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" config BOARD_IEI_PM_LX_800_R11 bool "PM LX-800-R11" +config BOARD_IEI_PM_LX2_800_R10 + bool "PM-LX2-800-R10"
endchoice
@@ -39,6 +41,7 @@ source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" source "src/mainboard/iei/pm-lx-800-r11/Kconfig" +source "src/mainboard/iei/pm-lx2-800-r10/Kconfig"
config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig new file mode 100644 index 0000000..194db4d --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -0,0 +1,71 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX2_800_R10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default iei/pm-lx2-800-r10 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX2-800-R10" + +config IRQ_SLOT_COUNT + int + default 3 + +config SCH3114_COM3_AUTO_DIR + bool "COM3 Automatic Direction Control" + default y + help + If selected, COM3 automatic direction control will + be enabled by default. + +choice + prompt "Core/GLIU Frequency" + default CORE_GLIU_500_266 + +config CORE_GLIU_500_266 + bool "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool "500MHz / 400MHz" + +endchoice + +endif # BOARD_IEI_PM_LX2_800_R10 diff --git a/src/mainboard/iei/pm-lx2-800-r10/chip.h b/src/mainboard/iei/pm-lx2-800-r10/chip.h new file mode 100644 index 0000000..d69f9b6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/cmos.layout b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout new file mode 100644 index 0000000..e09cfb6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +entries + # RTC + 0 384 r 0 reserved_rtc + # Coreboot + 384 1 e 3 boot_option + 385 1 e 3 last_boot + 386 4 r 0 reboot_bits + 390 3 e 4 baud_rate + 393 4 e 5 debug_level + 397 2 r 0 unused + # PM-LX2-800-R10 + 399 1 e 1 com3_auto_direction + 400 1 e 2 it8888_io_space0 + 401 1 e 2 it8888_io_space1 + 402 1 e 2 it8888_io_space2 + 403 1 e 2 it8888_io_space3 + 404 2 e 6 it8888_io_space0_speed + 406 2 e 6 it8888_io_space1_speed + 408 2 e 6 it8888_io_space2_speed + 410 2 e 6 it8888_io_space3_speed + 412 3 e 7 it8888_io_space0_size + 415 3 e 7 it8888_io_space1_size + 418 3 e 7 it8888_io_space2_size + 421 3 e 7 it8888_io_space3_size + 424 16 h 0 it8888_io_space0_addr + 440 16 h 0 it8888_io_space1_addr + 456 16 h 0 it8888_io_space2_addr + 472 16 h 0 it8888_io_space3_addr + 488 16 h 0 check_sum + +enumerations + # Yes / No + 1 0 No + 1 1 Yes + + # Enabled / Disabled + 2 0 Disabled + 2 1 Enabled + + # Normal / Fallback + 3 0 Fallback + 3 1 Normal + + # Console Baud Rate + 4 0 115200 + 4 1 57600 + 4 2 38400 + 4 3 19200 + 4 4 9600 + 4 5 4800 + 4 6 2400 + 4 7 1200 + + # Console Log Level + 5 0 Emergency + 5 1 Alert + 5 2 Critical + 5 3 Error + 5 4 Warning + 5 5 Notice + 5 6 Info + 5 7 Debug + 5 8 Spew + + # IT8888 Decoding Speeds + 6 0 Subtractive + 6 1 Slow + 6 2 Medium + 6 3 Fast + + # IT8888 Decoding Sizes + 7 0 1 + 7 1 2 + 7 2 4 + 7 3 8 + 7 4 16 + 7 5 32 + 7 6 64 + 7 7 128 + +checksums + checksum 384 487 488 diff --git a/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb new file mode 100644 index 0000000..f5721a3 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000ef25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0d0c0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "0" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 11.0 on end # IT8888 + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio # SMSC SCH3114 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.a on # Runtime Register + io 0x60 = 0x400 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c new file mode 100644 index 0000000..2bbf218 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include <arch/pirq_routing.h> + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 11 + +/* Links */ +#define L_PIRQN 0 +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +/* Bitmaps */ +#define B_LINKN (0) +#define B_LINK0 (1 << PIRQA) +#define B_LINK1 (1 << PIRQB) +#define B_LINK2 (1 << PIRQC) +#define B_LINK3 (1 << PIRQD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_AMD, /* Vendor */ + PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0x27, /* Checksum */ + { + [0] = { /* Host bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x01 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + }, + + [1] = { /* ISA bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [2] = { /* Ethernet */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + } + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def new file mode 100644 index 0000000..5920abc --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Name, Register, Enabled/Disabled, Speed, Size, Address. */ +IT8888_IO("it8888_io_space0", 0x58, 0, 0, 0, 0) +IT8888_IO("it8888_io_space1", 0x5c, 0, 0, 0, 0) +IT8888_IO("it8888_io_space2", 0x60, 0, 0, 0, 0) +IT8888_IO("it8888_io_space3", 0x64, 0, 0, 0, 0) +IT8888_IO("it8888_io_space4", 0x68, 0, 0, 0, 0) +IT8888_IO("it8888_io_space5", 0x6c, 0, 0, 0, 0) diff --git a/src/mainboard/iei/pm-lx2-800-r10/mainboard.c b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c new file mode 100644 index 0000000..170a67a --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <boot/tables.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" + +#if CONFIG_USE_OPTION_TABLE +# include "option_table.h" +#endif + +/* SCH3114 runtime register (RTR) address. */ +#define SCH3114_RTR_ADDR (0x400) +/* SP34 option register. */ +#define SCH3114_RTR_SP34_OPT (SCH3114_RTR_ADDR + 0x13) +/* H/W Monitoring register block index. */ +#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70) +/* H/W Monitoring register block data. */ +#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71) +/* H/W Monitoring Ready/Lock/Start register. */ +#define SCH3114_HWM_RLS_REG (0x40) +/* IT8888 PCI Vendor ID. */ +#define IT8888_PCI_VID (0x1283) +/* IT8888 PCI Device ID. */ +#define IT8888_PCI_DID (0x8888) + +static u16 opt(const char* option, u16 def_value) +{ +#if CONFIG_USE_OPTION_TABLE + u16 value = 0; + if (get_option(&value, option) != 0) + value = def_value; + return value; +#else + return def_value; +#endif +} + +static void init(struct device *dev) +{ + /* SCH3114: enable hardware monitor. */ + printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n"); + outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX); + outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT); + + /* SCH3114: COM3 Automatic Direction Control / nRTS control. */ + if (opt("com3_auto_direction", CONFIG_SCH3114_COM3_AUTO_DIR) != 0) { + printk(BIOS_INFO, "Enabling RS858 Auto Direction Control\n"); + outb(inb(SCH3114_RTR_SP34_OPT) | 0x03, SCH3114_RTR_SP34_OPT); + } + + /* IT8888. */ + device_t it8x = dev_find_device(IT8888_PCI_VID, IT8888_PCI_DID, 0); + if (!it8x) { + printk(BIOS_ERR, "IT8888 not found\n"); + return; + } + + u32 cfg = 0; +#define IT8888_IO(name, reg, dena, dspeed, dsize, daddr) \ + if (opt(name, dena) != 0) { \ + cfg = (1 << 31); \ + cfg |= opt(name "_addr", daddr); \ + cfg |= opt(name "_speed", dspeed) << 29; \ + cfg |= opt(name "_size", dsize) << 24; \ + } else { \ + cfg = 0; \ + } \ + pci_write_config32(it8x, reg, cfg); + +#include "it8888_io.def" +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX2-800-R10 Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c new file mode 100644 index 0000000..da0c769 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Ricardo Martins rasmartins@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> + +#include <spd.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <arch/llshell.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <southbridge/amd/cs5536/early_smbus.c> +#include <southbridge/amd/cs5536/early_setup.c> +#include <superio/smsc/smscsuperio/early_serial.c> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#if CONFIG_CORE_GLIU_500_400 +# define PLLMSRhi 0x0000059c +#elif CONFIG_CORE_GLIU_500_333 +# define PLLMSRhi 0x0000049c +#else +# define PLLMSRhi 0x0000039c +#endif + +#define PLLMSRlo 0x07de000 + +#include <northbridge/amd/lx/raminit.h> +#include <northbridge/amd/lx/pll_reset.c> +#include <northbridge/amd/lx/raminit.c> +#include <lib/generic_sdram.c> +#include <cpu/amd/geode_lx/cpureginit.c> +#include <cpu/amd/geode_lx/syspreinit.c> +#include <cpu/amd/geode_lx/msrinit.c> + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Enable COM3. */ + device_t dev = PNP_DEV(0x2e, 0x0b); + u16 port = dev >> 8; + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + outb(0xaa, port); + + report_bist_failure(bist); + + pll_reset(1); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +}