V2 EPIA - IDE compat mode, RAM init, and early MTRR

[SONE Takeshi]

Attached patch fixes IDE compatibility mode (so FILO works),
and RAM initialization, so the DIMM on the second slot works.
SPD is not used by this patch, we have to figure out how to 
type MA mapping by SPD (see the comment in the code).
Maybe I will work on SPD-based RAM timing.
earlymtrr.c should go to src/cpu/p6 so the XIP works.
The change in src/cpu/p6/mtrr.c just reverse the change made by
Eric for K8..