[coreboot] Patch set updated for coreboot: e685c0c AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio

[Jens Rottmann]

Jens Rottmann ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2454

-gerrit

commit e685c0cc2b4f2f69735ec5b8bdae0e0271bc02e6
Author: Jens Rottmann 
Date:   Tue Feb 19 15:01:06 2013 +0100

AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio

The power up default for 14M_25M_48M_OSC is 14 MHz. sb800/bootblock.c changes
    this to 48 MHz, which is the correct value for almost all SIOs.  However, not
    for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz.  We could
    switch back to 14 in the mainboard's romstage.c, but then the clock frequency
    would change twice.

This patch skips the SB800 clock switch if the SIO is smscsuperio.  This does
    not affect any boards currently in the repository (yet).

Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
    Signed-off-by: Jens Rottmann 
---
 src/southbridge/amd/cimx/sb800/bootblock.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 0a339b0..ac92c05 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -97,10 +97,17 @@ static void enable_clocks(void)
    reg8 &= ~(1 << 1);
    outb(reg8, 0xCD7);

-	// Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz)
+	// Program SB800 MiscClkCntrl register to configure clock output on the
+	// 14M_25M_48M_OSC ball usually used for the Super-I/O.
+	// Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz,
+	// which is the SB800's power up default.  We could switch back to 14
+	// in the mainboard's romstage.c, but then the clock frequency would
+	// change twice.
    reg32 = *acpi_mmio;
-	reg32 &= ~((1 << 0) | (1 << 2));
-	reg32 |= 1 << 1;
+	reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default)
+#ifndef CONFIG_SUPERIO_SMSC_SMSCSUPERIO
+	reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz
+#endif
    *acpi_mmio = reg32;
 }