Hello,
attached is the patch which implements the mem speed table, mainboards describe it's mem speed ability in mem_controller structure as the following example:
static const struct mem_controller cpu[] = { { .node_id = 0, .f0 = PCI_DEV(0, 0x18, 0), .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), .channel0 = { (0xa<<3)|0, (0xa<<3)|2, (0xa<<3)|4, (0xa<<3)|6 }, .channel1 = { (0xa<<3)|1, (0xa<<3)|3, (0xa<<3)|5, (0xa<<3)|7 }, .memclk_conf = { {4, 4, 2, 0, 0, 200}, /* 200M for: 4x1rank, 2x1rank + 2x2rank, etc */ {4, 4, 0, 2, 0, 200}, {4, 4, 0, 0, 2, 200}, {8, 8, 8, 8, 8, 166}, /* 166M for other case */ {0, 0, 0, 0, 0, 0}, /* the end */ } }, };
Tao