Hi,
On Sat, Jun 20, 2009 at 02:34:24AM +0100, Andrew Morgan wrote:
Here is the output of 'lspci -tvnn', 'superiotool -dV', 'getpir', and 'mptable' run on the (beautifully named) Soyo SY-6BA+ III motherboard.
Thanks, please see attached patch for a first attempt at a coreboot port. The board is (of course) similar to all other 440BX boards in svn. I used 256 KB as ROM chip size, is that correct for your board?
Also, the Realtek NIC is onboard I assume? Or is it PCI? I assumed onboard for now.
Apply the patch like this to an svn checkout: --------------------------------------------- patch -p0 < v2_soyo_board.patch
Building: --------- cd targets ./buildtarget soyo/sy-6ba-plus-iii cd soyo/sy-6ba-plus-iii/sy-6ba-plus-iii cp ~/filo.elf payload.elf make
The coreboot.rom file (256 KB) which is generated is what you want to flash using flashrom (see http://coreboot.org/Flashrom). Make sure you only attempt this if you know flashrom supports your board and if you have a working spare backup chip. Join us on IRC for help with this, if needed.
The filo.elf is the payload which you choose, see wiki.
Then, insert exactly one (64 MB or bigger) DIMM into slot 0, attach a null-modem cable to COM1 and some other box where you use minicom (115200 8n1) to view serial debug output which you'll hopefully get.
If you insert a PCI graphics card and are lucky, it might also get initialized correctly, but serial is probably the safer bet for the first test.
Godd luck, Uwe.