5. + /* Enable extended apic id's and second core */ + val = pci_read_config32(dev_f0, 0x68); + val |= (1 << 18) | (1 << 17) | ( 1 << 5); + pci_write_config32(dev_f0, 0x68, val);
ext apic id mode is only need to enable for 8 way dual core system.
6. incohere_ht.c overwrite my new changes need to be roll back. 7. debug.c need to rollback.
YH
On 8/9/05, yhlu yinghailu@gmail.com wrote:
- it's good, to move hardware mem hole support from raminit.c to
northbridge.c, So it will be dynamically. but problem is it will use more MTRRs. So carry_on should be calculated in some way...
YH
On 8/9/05, yhlu yinghailu@gmail.com wrote:
- are you sure the node1/core0 could start node1/core1?
Accorinding to my testing last year, node1/core1 only can be started by node0/core0.
YH
On 8/9/05, yhlu yinghailu@gmail.com wrote:
- you overwite the enable ext id and apic id lifting
YH
On 8/9/05, yhlu yinghailu@gmail.com wrote:
- write_irq_tables changes is overwrite by you. that will broke all
other Opteron MB. Please change that back.
YH
On 8/9/05, Jason Schildt jschildt@lnxi.com wrote:
All,
I've just made a commit up to the public repository from the Linux Networx repository mirror. The changes only effect Opteron single/dual core and hdama board specific code. Regards,
--jason--
--
Jason W. Schildt LinuxBIOS Software Engineer Linux Networx
LinuxBIOS mailing list LinuxBIOS@openbios.org http://www.openbios.org/mailman/listinfo/linuxbios