On 11/10/2010 07:30 PM, Scott Duplichan wrote:
-----Original Message----- From: Joseph Smith [mailto:joe@settoplinux.org] Sent: Wednesday, November 10, 2010 05:42 PM To: Scott Duplichan Cc: 'Patrick Georgi'; coreboot@coreboot.org Subject: Re: [coreboot] [PATCH] Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems
]On 11/10/2010 06:18 PM, Scott Duplichan wrote: ]> ] On i945, UMA is done by providing a fixed resource. I don't think any ]> ] other changes were necessary (see src/northbridge/intel/i945/northbridge.c) ]> ]> I took a look at the i945 code and found the AMD code also adds the exact ]> same fixed resource for the UMA area. What I cannot figure out is how this ]> can reduce the WB DRAM range so that the UMA memory ix excluded. ]> ]> If I test with 2GB installed and a 256 MB frame buffer, function add_uma_resource ]> is called with the expected arguments: Adding UMA memory area, base=70000000 size=10000000 ]> ]> Later, set_var_mtrr_resource is passed a range of c0000-7fffffff. The existing ]> coreboot code assumes this range has already had the UMA part removed, and ]> adds it back: ]> ]> // Increase the base range and set up UMA as an UC hole instead ]> var_state.range_sizek += (uma_memory_size>> 10); ]> ]> What logic should deduct the reserved range from the DRAM range before ]> this code runs? ]> ]Hmm. The UMA resource should be in high memory. And code should say if ]UMA high memory resource is used do not allocate c0000. Interesting.....
I think I can explain this part. The message "Adding UMA memory area, base=70000000 size=10000000" refers to the physical address of the DRAM that becomes unavailable due to UMA. This DRAM is never accessed using this physical address. It is accessed through the frame buffer bar, which gets assigned an address between top of memory and 4GB, such as E8000000.
Not so sure about AMD chips but I know Intel chips reserve memory just below 4Gb for vga buffer. As for resource ranges Intel chips reserve a low memory range for VESA IO registers and a high memory range for GMCH MMIO registers. Hope that helps.