Hi all,
I actually managed to fix the problem with loading elf image, it was faulty filo, but I still have about 10sec delay from power cycle before coreboot starts logging. I use regular PS, and original BIOS starts up immediately. I use regular power switch now, but it will be ACPI signal in the future.
So actually my original BIOS proceeds quicker than my current coreboot :(
Thanks for explaining that memory part of the log, now it makes perfect sense.
One more question, or idea; is it going to be worthwhile to modify scripts (and Config.lb options) to have ability to merge VideoBIOS (optionally) into rom image?
... and another one; Config.lb has ROM_SIZE , and ROM_SECTION_SIZE variables. I noticed that these 2 cannot have the same value (compilation fails saying "Integer constant too large" - division by zero?), but there are cases when I need to have both of them the same (single section in the rom image). Is it a bug?
I'm new to this project, thus my questions are popping, but I didn't find my answers anywhere else.
Thanks
Hi Jacek,
On Wed, Feb 20, 2008 at 08:00:32PM -0600, Jacek Chruscik wrote:
I include log from coreboot startup on EPIA MII with 1.2GHz C3 processor.
This board should work just fine.
First of all it fails to run my FILO payload, second, I noticed it may fail on RAM check-up, it sees only 16MB out of 256 or 512 (tried both)
No, it does actually see all your RAM. More below.
Furthermore, I have to wait about 10 sec form power cycle for coreboot to send anything through serial line.
This should not happen. What kind of power supply are you using and how do you power on the board when starting coreboot?
Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10
One (01) bank is found, bank 0, which has 16 (10) * 16MB = 256MB.
Note that the two-digit value last on each line here is hex but is missing a leading 0x. :\
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3
Can not load ELF Image.
Could you send us the output from your coreboot make?
//Peter
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