26 May
2010
26 May
'10
3:16 p.m.
Stefan Reinauer stefan.reinauer@coresystems.de writes:
That alone won't do it,.. There's the AMD specific MSR and %gs is not set to MMCONFIG_BASE on other chipsets/cpus. Not sure what to do about the MSR,... the %gs thing should probably fixed by setting up %gs in a central place somewhere.
If we move the MMCONF area into the 32-bit reachable range, we don't need to mess around with %gs. The other AMD specfic MSRs are localized to AMD specfic files, I believe.
--
Arne.