On Mon, December 11, 2017 12:56 am, awokd wrote:
I got it [after many days of research and trial]! I had to update src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c from:
STATIC CONST UINT16 ROMDATA CpuF15TnMicrocodeEquivalenceTable[] = { 0x6101, 0x6101, 0x6100, 0x6100 };
// Unencrypted equivalent STATIC CONST UINT16 ROMDATA
CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] =
{ 0x6101, 0x6901, 0x6100, 0x6900 };
TO:
STATIC CONST UINT16 ROMDATA CpuF15TnMicrocodeEquivalenceTable[] = { 0x6131, 0x6101, 0x6101, 0x6101, 0x6100, 0x6100 };
// Unencrypted equivalent STATIC CONST UINT16 ROMDATA
CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] =
{ 0x6131, 0x6901, 0x6101, 0x6901, 0x6100, 0x6900 };
Is there a newbie primer somewhere on how to make a commit?
Now I am seeing patch level 0x0600110f on all CPUs, and my Xen/Qubes HVMs start without freezing the entire machine.
Still haven't been able to figure out how to get them to patch level 0x06001119 like under the OEM firmware. I found the blob corresponding to that patch level in there as well as in the stock microcode_amd_fam15h.bin 3rdparty blob. From looking at src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h it seems as though microcode updates might be hardcoded (F15_TN_UCODE_10F, for example). Would I need to hardcode my newer version too, or am I reading it wrong?
I did some quick testing with device passthrough under Qubes and it doesn't seem to be working but I need to spend more time on it.
Got the CPU patch level to 0x06001119 by converting the blob to hex and dumping it over top of the hex in src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c. Kind of an ugly hack but I was having trouble following the microcode update logic in there; it's scattered all over. Is there an open source graphical IDE that makes it easier? What's the best approach to turn this into a commit? Please cc list if you reply, my email provider is having trouble.
Anyways, passthrough is working now too. The Atheros Ethernet and wireless controllers support PCI strict reset, but not the built in USB controllers. This might be a dumb question but is there a way to enable that functionality in Coreboot, or is it a hardware limitation?
Thanks to all who replied to my earlier emails, it definitely helped.