Author: stepan Date: Sun Apr 25 23:43:29 2010 New Revision: 5499 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5499
Log: a single place for the romstage stack for copy_and_run. geode lx and amd opteron don't use this yet.
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Stefan Reinauer stepan@coresystems.de
Added: trunk/src/include/cpu/x86/stack.h Modified: trunk/src/arch/i386/init/crt0_prologue.inc trunk/src/arch/i386/init/crt0_romcc_epilogue.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc
Modified: trunk/src/arch/i386/init/crt0_prologue.inc ============================================================================== --- trunk/src/arch/i386/init/crt0_prologue.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/arch/i386/init/crt0_prologue.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -18,6 +18,7 @@ */
#include <cpu/x86/post_code.h> +#include <cpu/x86/stack.h>
.section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits
Modified: trunk/src/arch/i386/init/crt0_romcc_epilogue.inc ============================================================================== --- trunk/src/arch/i386/init/crt0_romcc_epilogue.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/arch/i386/init/crt0_romcc_epilogue.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -14,16 +14,7 @@ movl %ebp, %esi
- /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run
Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -30,6 +30,7 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize)
+#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h>
/* Save the BIST result */ @@ -398,16 +399,7 @@ movl %ebp, %esi
- /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run
Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -21,6 +21,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h>
@@ -256,16 +257,7 @@ movl %ebp, %esi
- /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run
Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -21,6 +21,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h>
@@ -256,16 +257,7 @@ movl %ebp, %esi
- /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run
Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -21,6 +21,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h>
@@ -270,16 +271,7 @@ movl %ebp, %esi
- /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run
Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/via/car/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -28,7 +28,7 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE
- +#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h>
/* Save the BIST result */ @@ -270,16 +270,7 @@ movl %ebp, %esi
- /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run
Added: trunk/src/include/cpu/x86/stack.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/x86/stack.h Sun Apr 25 23:43:29 2010 (r5499) @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __CPU_X86_STACK_H +#define __CPU_X86_STACK_H + +/* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M-64K of memory that we + * preserve for suspend/resume. This is basically HIGH_MEMORY_SAFE (see + * cbmem.h) + */ + +#define ROMSTAGE_STACK_OFFSET ( (1024 - 64) * 1024 ) +#define ROMSTAGE_STACK (CONFIG_RAMBASE + ROMSTAGE_STACK_OFFSET) + +#endif