Hi Jürgen,
On 14.07.2008 10:21, Juergen Beisert wrote:
Hi Carl-Daniel,
On Montag, 14. Juli 2008, Carl-Daniel Hailfinger wrote:
thanks a lot for the code.
On 13.07.2008 22:50, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Carl-Daniel Hailfinger wrote:
[CAR for GX1]
Its not adapted to v2 nor v3. Its only an example, how to do it for CPUs with these special cache test registers (like older i486 and the Geode GX1).
You say "older i486". Does that mean newer i486 have different registers?
No, that's not what I mean. All i486 are "old", aren't they? ;-) My amd486 datasheet tells me, this CPU has such registers. I believe the old Intel i486s also have such registers (but I'm not sure).
Thanks for clarifying.
After running this program, you have (a very fast) RAM at physical address __car_data_dst up to (__car_data_dst + __car_size). These two symbols are generated by my linker script. I'm using this code in my current u-boot-v2 development for ia32.
Note: This code must run with *disabled* cache and this piece of RAM only exists and is useable, _until_you_enable_the_cache_! Note also: You should locate this CAR area in the regular SDRAM area, because when you enable the cache (after SDRAM controller initialisation), the cache unit will flush its content to the SDRAM. It will fail badly if at the same physical address is no real memory to write/flush to.
Hm. I thought a self-copy followed by a WBINVD was required to transfer the cache contents to the SDRAM.
But also the WBINVD will fail, if at the physical mapping address is no valid device (like SDRAM or PCI...). In this case you must use the INVD instruction instead. But I believe you know what you are doing ;-)
Yes, my question was mostly about the lack of WBINVD in your code. Having a CAR area not backed by SDRAM would be "interesting", not to say stupid in our case.
I think I have figured out where to merge your code into the existing Geode LX CAR code.
Regards, Carl-Daniel