Re: [coreboot] AMD cache setup is broken

[Arne Georg Gleditsch]

Arne Georg Gleditsch  writes:
> /* Clear ClLinesToNbDis */
> msr = rdmsr(BU_CFG2_MSR);
> msr.lo &= ~(1 << 15);
> wrmsr(BU_CFG2_MSR, msr);

On an slightly unrelated note; do we want to clear bit 35 here as well?
At the moment, this is only done for the BSP, causing the MSR settings
to be inconsistent after boot.  I see that errata 343 indicates that
this should be cleared after CAR is disabled, so it might not matter all
that much for the APs...