-----Original Message----- From: coreboot-bounces+mylesgw=gmail.com@coreboot.org [mailto:coreboot- bounces+mylesgw=gmail.com@coreboot.org] On Behalf Of Uwe Hermann Sent: Wednesday, September 30, 2009 7:31 PM To: coreboot@coreboot.org Subject: [coreboot] Boot issues (CBFS?) on VIA pc2500e
Hi,
tried to boot-test the VIA p2500e yesterday, but tried a manual non-kconfig build first, and that one doesn't successfully boot anymore and thus needs to be fixed first.
The cfbs output was (I used a FILO payload):
Name Offset Type Size fallback/payload 0x0 payload 85864 fallback/coreboot_ram 0x14fc0 stage 35069 0x1d900 null 337592
Here's a bootlog, there's a "hang" at the end, no further output on serial afterwards. Any ideas what the issue may be?
It doesn't look like a place I would expect CBFS to be the issue.
tomk is 0x80000 tom: 20000000, high_tables_base: 1fff0000, high_tables_size: 10000
512M of RAM = 0x20000000, 64K for high tables. ...
High Tables Base is 1fff0000. Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x1fff0000... done. Wrote the mp table end at: 000f0410 - 000f0568 Wrote the mp table end at: 1fff0410 - 2001040e
Writing high tables above RAM! Why is the high MP table so much larger than the low one?
Moving GDT to 0x20010800...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum d3dd New low_table_end: 0x00000518 Now going to write high coreboot table at 0x20010c00 rom_table_end = 0x20010c00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x20010c00 to 0x20020000
And more writing above RAM.
I don't know that that is the cause of your trouble, but it isn't good. An easy thing to try would be to increase high_tables_size to 0x40000 and see if you get anything different. I'm surprised that your mp table is so large. Maybe that's where the real problem is?
Thanks, Myles