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VIA EPIA - Status
by OliverArnold＠via.com.tw 05 Dec '02

05 Dec '02

hello ng, i just want to check, what is the status of the epia port? oliver

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2.4.19 and sparse e820 map
by Ronald G. Minnich 05 Dec '02

05 Dec '02

The first problem is this: BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000000bcc (reserved) BIOS-e820: 0000000000000bcc - 00000000000a0000 (usable) BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved) BIOS-e820: 0000000000100000 - 0000000020000000 (usable) BIOS-e820: 0000000100000000 - 0000000120000000 (usable) 3712MB HIGHMEM available. 896MB LOWMEM available. those MEM numbers are quite bogus. The second problem is that it can't find the initrd in the image. On a good load the initrd is at 2000a000 i.e. 512MB+some, and that puts it on this mem right at memory that doesn't exist. I think it is getting confused early in the game and ending up with an initrd somewhere bogus. ron

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linux 2.4.19 and E820 problems CONFIRMED
by Ronald G. Minnich 04 Dec '02

04 Dec '02

I have just confirmed that 2.4.19 won't work at all with the memory split. I set remap_high to disable in cmos and the node is now workig correctly. I think I'm going to have a CONFIG option to disable this completely, since if it gets turned on accidently I have an unbootable node. Comments? ron

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common flash hw write enable methods
by Andrew Kohlsmith 04 Dec '02

04 Dec '02

So I've got linuxbios booting inside Bochs and I feel I'm confident enough to roll the dice and burn it to a real board (TSSOP package, no sockets) using /dev/bios. After some head-scratching, I realize that the hardware RP# and VPP are tied together, and at a logic low, preventing any flash attempts. These are pins 10 and 11 on the TSSOP part. :-( Now I imagine that these are tied to a MOSFET to +12V which is run off of a GPIO pin. The question is, without tracing an 8-layer board out to try and identify how exactly reflash is enabled, how to reflash this? I can always cut the traces and hard-wire to +12V but I'd like to see if I can't do this programmatically. I have a number of boards I want to use and hardware hacking is something I'd like to avoid doing if possible. Now I know that every motherboard is different and that there may be other things locking me out, but generally speaking is there an "industry standard" way of enabling/disabling BIOS reflash? It's currently a PhoenixBIOS, so I imagine if I located a reflash tool and ran it in a Bochs session with a lot of I/O debugging I could figure out what it's doing but before I embark on that I'd like to see if anyone has any hints that may save me a lot of time. Regards, Andrew

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question on e7500 sizeram
by Ronald G. Minnich 04 Dec '02

04 Dec '02

freebios/src/northbridge/intel/E7500/northbridge.c In this file there is a variable called remap_high. I assume the function of this is to remap the high memory (512MB) so it is contiguous with the low 512MB. Even when remap_high is true, on -current, I end up with two 512MB segemnts, one at 0 and one at 4 GB. Anybody have any idea as to why this would happen? It's confusing 2.4.19 from what I can see. ron

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Re: Question regarding instructions...
by Nathanael Noblet 04 Dec '02

04 Dec '02

Hello again, So I ordered 6 of the flash chips and got a PLCC removal tool. I'm ready to start getting this working on my machine. I am still unclear as to the steps to proceed in order to do that. I have looked at the tiara source, there seems to be quite a bit there so that is promising. Where I become confused is where to put my code and such, how to break it up. Looking at making a Config file, it says to set the target (for example winfast) does that mean I need to make my own for arbor (maker of this SBC)? and then all the mainboard/model stuff as well. How do I know where everything is to go? Are there any docs relating to how to proceed to get all the devices setup and placement of files. There seems to be quite a few directories with nothing in them and that is confusing as well. I have the output of lspci -vvvv and the datasheet for the sis530 that is the chipset on this board. I don't see anything similar to the superio chips that seem to be related to the other sis boards etc... So basically I'm wondering: 1) What are the basic things I need to implement / create to get linuxbios up and compiled etc.. 2) Is there anything that better explains the directory/file structure of the source tree? a) if there isn't, then how can I determine what to put where? I think that is it for now. Thanks for the help so far, this is exciting, I hope to be able to help the project out by getting LinuxBIOS on one more box, albeit a somewhat older one (but good for embedded development). :) -- Nathanael Noblet Gnat Solutions 4604 Monterey Ave NW Calgary, AB T3B 5K4 T/F 403.288.5360 C 403.809.5368 http://www.gnat.ca/

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How to make a supermicro linuxbios?
by lawrence 03 Dec '02

03 Dec '02

Hi all: I am trying to make a ROM of supermicro p4dpe. I got a romimage of 448K which is cat from payload.block(400K) and linuxbios.rom(48K). But at the end of the romimage i can not see the first far jump instruction EAh, so I suppose it is why the rom does not work on my board. What's wrong? Thanks, Lawrence

2 1

remap_high in the e7500 northbridge
by Ronald G. Minnich 03 Dec '02

03 Dec '02

Does this mean remap memory to 4GB + or remap high memory to low memory space. I think I have been misunderstanding it. ron

2 2

E7500
by Ronald G. Minnich 03 Dec '02

03 Dec '02

Status: - working fallback linuxbios that was built on redhat 7.3 w/ gcc 2.96 (bogus redhat version :-) - trying to get a supermicro p4dpe to work on redhat 8.0 - kernel+initrd is loaded from IDE-flash via etherboot. This is a bproc "phase 1" kernel, and will download and boot a "phase 2" kernel. The phase 1 kernel is non-smp, and should use PIRQ tables or similar to set up IRQs, it turns out. It appears not to be MP-table aware. The phase 2 kernel is SMP- and MP-table aware. If I build linuxbios with gcc 3.2, it loads the phase 1 kernel but ... that kernel can't find any interrupts for the myrinet card. If I build linuxbios with gcc 2.96, that kernel can find interrupts and download the phase 2 kernel. The phase 2 kernel finds the MP table and gets everything ready to go, but panics when trying to set up the initrd for reasons that are not clear. It seems to think it has 4 GB memory, when it fact it has 1 GB memory with a big memory hole. Can Linux 2.4.19 handle this kind of sparse memory map? right now, experience is saying "no", although I thought this was working. Now I think I need to look at the PIRQ table as compiled by gcc 3.2. The MP table seems to be created just fine. Interesting. ron

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GCC 3.2 can now build linuxbios
by Ronald G. Minnich 03 Dec '02

03 Dec '02

The simple change I made to irq_table did the trick. Myrinet drivers are now finding their IRQ. Now to find the next problem ... RAMDISK: Couldn't find valid RAM disk image starting at 0. Freeing initrd memory: 741k freed Kernel panic: VFS: Unable to mount root fs on 01:00 :-) ron

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