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Intel IDF - EFI to replace BIOS
by Bari Ari 21 Feb '03

21 Feb '03

Looks like Intel is predicting EFI to replace BIOS soon from the presentation at the IDF this week. http://news.zdnet.co.uk/story/0,,t269-s2130826,00.html http://slashdot.org/article.pl?sid=03/02/20/189208 http://www.anandtech.com/showdoc.html?i=1791&p=2 http://www.intel.com/technology/efi/index.htm Bari

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RE: how to choice fallback or normal image?
by Terry B. Chen 21 Feb '03

21 Feb '03

I read the code in cmos_failover.inc But I don’t understand that RTC_BOOT_BYTE bit 1 gets the value from bit 0, the program clear bit 0 every time. But When to set the bit0 to 1, it will make the code jump to normal image next time? I search 0x70(cmos index) in all but I cant find when set bit 0 to 1? -----Original Message----- From: steven james [mailto:pyro@linuxlabs.com] Sent: 2003年2月20日 23:27 To: Terry B. Chen Cc: linuxbios(a)clustermatic.org Subject: Re: how to choice fallback or normal image? Greetings, Several conditions need to exist for the primary image to be used. The code looks at the RTC register to check for indication of power failure (either battery dead, or clear CMOS jumper set), then the CMOS checksum is checked. If both tests show that CMOS is valid, then check the RTC_BOOT_BYTE. First, bit 0 is moved to bit 1 and bit 0 is cleared. Then, if bit 1 is set, call the primary (normal image), That is done so that if the boot fails for some reason, it will choose the fallback image next time. It is also possible to cause a fallback boot by setting the clear CMOS jumper. The RTC_BOOT_BYTE is not included in the checksum since it will be changed wi8th every boot. Note that on some boards, the CMOS checksum is skipped. G'day, sjames The RTC_BOOT_BYTE On Thu, 20 Feb 2003, Terry B. Chen wrote: > Dear all: > I was puzzled by the fallback and normal image in s2722 > (e7500), I am sorry to ask so simple question. When shall we use the > fallback image and when shall we use the normal image? How you control > which to run? > The register DRC (7c) bit 29(Init complete) seem not to be set > after memory initialization complete. am I right? > Thank you! > -- -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office 404.577.7747 fax 404.577.7743 -----------------------------------------------------------------------

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How to initialize USB controller in LinuxBios?
by riskin＠263.net 20 Feb '03

20 Feb '03

Hi,ollie, My kernel is "2.2.14",so I need to initialize USB controller in LinuxBios. But,I don't know how to correctly initialize USB controller in LinuxBios on the sis630e chipset. I have checked the USB pci config space on the sis630e chipset, so I assigned "I/0" addresses "0xd001<<12" and "0xd8001<<12". And,the function number of the tow USB controller is 2 and 3. So,I modified LinuxBios like following: void pci_usb_enable(unsigned bus, unsigned slot, unsigned int irq) { unsigned functNum; struct pci_dev *pdev; unsigned char line; unsigned char readback; u32 io[2]={0xd001<<12,0xd801<<12}; for (functNum = 2; functNum < 4; functNum++) { pdev = pci_find_slot(bus, (slot << 3) + functNum); if (pdev) { pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &line); printk_debug("USB PIN: %d\n",line); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, \ io[functNum-2]); pci_write_config_byte(pdev, PCI_COMMAND, \ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); if ((line >= 1) && (line <= 4)) { printk_debug("Assigning usb IRQ %d to %d:%x.%d\n", \ irq, bus, slot, functNum); pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,\ irq); pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, \ &readback); printk_debug(" Readback = %d\n", readback); } } } } ... pci_usb_enable(0,1,0xa); ... After done this,I looked up /proc/pci: PCI devices found: Bus 0, device 0, function 0: Host bridge: Silicon Integrated Systems Unknown device (rev 33). Vendor id=1039. Device id=630. Medium devsel. Master Capable. Latency=64. Non-prefetchable 32 bit memory at 0xf8000000 [0xf8000000]. Bus 0, device 0, function 1: IDE interface: Silicon Integrated Systems 85C5513 (rev 208). Fast devsel. IRQ 14. Master Capable. Latency=16. I/O at 0x2c00 [0x2c01]. Bus 0, device 1, function 0: ISA bridge: Silicon Integrated Systems 85C503 (rev 0). Medium devsel. Master Capable. No bursts. Bus 0, device 1, function 1: Ethernet controller: Silicon Integrated Systems Unknown device (rev 131). Vendor id=1039. Device id=900. Medium devsel. Fast back-to-back capable. IRQ 9. Master Capable. Latency=64. Min Gnt=52.Max Lat=11. I/O at 0xb000 [0xb001]. Non-prefetchable 32 bit memory at 0xfc108000 [0xfc108000]. Bus 0, device 1, function 2: USB Controller: Silicon Integrated Systems 7001 USB (rev 7). Medium devsel. Fast back-to-back capable. IRQ 10. Master Capable. Latency=64. Max Lat=80. Non-prefetchable 32 bit memory at 0xd001000 [0xd001000]. Bus 0, device 1, function 3: USB Controller: Silicon Integrated Systems 7001 USB (rev 7). Medium devsel. Fast back-to-back capable. IRQ 10. Master Capable. Latency=64. Max Lat=80. Non-prefetchable 32 bit memory at 0xd801000 [0xd801000]. Bus 0, device 2, function 0: PCI bridge: Silicon Integrated Systems 5591/5592 AGP (rev 0). Fast devsel. Master Capable. No bursts. Min Gnt=8. Bus 0, device 9, function 0: Bridge: Texas Instruments Unknown device (rev 0). Vendor id=104c. Device id=ac60. Medium devsel. IRQ 5. Non-prefetchable 32 bit memory at 0xfc10b000 [0xfc10b000]. Non-prefetchable 32 bit memory at 0xfc100000 [0xfc100000]. Non-prefetchable 32 bit memory at 0xfc10c000 [0xfc10c000]. Bus 0, device 11, function 0: Ethernet controller: Realtek 8139 (rev 16). Medium devsel. Fast back-to-back capable. IRQ 10. Master Capable. Latency=64. Min Gnt=32.Max Lat=64. I/O at 0x2400 [0x2401]. Non-prefetchable 32 bit memory at 0xfc10d000 [0xfc10d000]. Bus 0, device 13, function 0: Ethernet controller: Realtek 8139 (rev 16). Medium devsel. Fast back-to-back capable. IRQ 9. Master Capable. Latency=64. Min Gnt=32.Max Lat=64. I/O at 0x2800 [0x2801]. Non-prefetchable 32 bit memory at 0xfc10e000 [0xfc10e000]. Bus 1, device 0, function 0: VGA compatible controller: Silicon Integrated Systems Unknown device (rev 33). Vendor id=1039. Device id=6300. Medium devsel. Fast back-to-back capable. BIST capable. Prefetchable 32 bit memory at 0xf0000000 [0xf0000008]. Non-prefetchable 32 bit memory at 0xfc000000 [0xfc000000]. I/O at 0x1000 [0x1001]. I didn't find The "I/O" addresses of USB controller. So,is there other things need to be done to initialize USB controller correctly? Could you help me? Thanks, riskin ========================== 263电子邮件－信赖邮自专业

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how to choice fallback or normal image?
by Terry B. Chen 20 Feb '03

20 Feb '03

Dear all: I was puzzled by the fallback and normal image in s2722 (e7500), I am sorry to ask so simple question. When shall we use the fallback image and when shall we use the normal image? How you control which to run? The register DRC (7c) bit 29(Init complete) seem not to be set after memory initialization complete. am I right? Thank you!

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ALI M1429L 386/486 mem ctlr datasheet - anyone have it?
by Jeremy Jackson 20 Feb '03

20 Feb '03

I'm looking at bits and pieces of a TI/Acer Extensa 455T laptop, and I would like to try LinuxBIOS for it if I can get the datasheet. I wrote ALI, but I'm not getting my hopes up. -- Jeremy Jackson <jerj(a)coplanar.net>

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option_table ?
by Terry B. Chen 20 Feb '03

20 Feb '03

Hi all, I have a question about option table; the utility "build_opt_tbl.c" will give us an option_table.c automatically, but where is the option_table [ ] used? How to control my Linuxbios go to fallback or normal image? We always run in fallback image. Can someone give me some suggestions? The code is in file reset_test.inc and cmos_failover.inc. The code total is " #define MCH_DRC 0x7C #define DRC_IC (1 << 29) /* If I have already booted once skip a bunch of initialization */ /* To see if I have already booted I check to see if memory * has been enabled. */ movl $MCH_DRC, %eax PCI_READ_CONFIG_DWORD testl $DRC_IC, %eax setnz %al testb %al, %al jz __failover_boot __failover_reset: movb $RTC_BOOT_BYTE, %al outb %al, $0x70 inb $0x71, %al testb $(1<<1), %al jnz __normal_image jmp __cpu_reset __failover_boot: /* See if the cmos clear jumper has been set */ movl $((RTC_DEVFN << 8) | GEN_PMCON_3), %eax PCI_READ_CONFIG_DWORD testl $RTC_FAILED, %eax jz __cs_test /* There are no impossible values, no checksums * so just trust whatever value we have in the * cmos. */ __rtc_failed: movb $RTC_BOOT_BYTE, %al outb %al, $0x70 inb $0x71, %al andb $0xfc, %al outb %al, $0x71 jmp __cs_test /* test the checksum */ __cs_test: movl $77,%ecx xor %ebx,%ebx movl $RTC_BOOT_BYTE, %edx 1: addl $1, %edx movl %edx, %eax outb %al, $0x70 inb $0x71, %al addl %eax,%ebx subl $1,%ecx jnz 1b not %ebx addl $1, %edx movl %edx, %eax outb %al, $0x70 inb $0x71, %al movb %al,%ch addl $1, %edx movl %edx, %eax outb %al, $0x70 inb $0x71, %al movb %ch,%ah cmpw %ax,%bx jz __rtc_ok /* Set to fall back mode */ movb $RTC_BOOT_BYTE, %al outb %al, $0x70 inb $0x71, %al andb $0xfc, %al outb %al, $0x71 /* The byte is o.k. see where to go */ __rtc_ok: movb $RTC_BOOT_BYTE, %al outb %al, $0x70 inb $0x71, %al /* Transfer the boot bit from bit 0 to bit 1. * And clear bit 0 so that unless we say it works we * fallback to the other bios image immediately. */ movb %al, %bl andb $0xfc, %al andb $1, %bl shlb %bl orb %bl, %al outb %al, $0x71 testb $(1<<1), %al jnz __normal_image

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help!!!who can explain the interface between linuxbios and linux.
by �� 19 Feb '03

19 Feb '03

dear all: I have developed a linuxbios debug system succefully.I introduced gdb stub into my system. In my system ,developers can debug linuxbios at source code level. I setup the stub at the beginning of the begin of the function of hardwaremain, the first c function.Now the system can excute the function of "step",'step into" "step out" ,"breakpoint"and so on. but the system has not been tested fully. I wonder if my design is usefull to others. by the way, I have several question.I will appreciate anyone's any idea! my question are as follows: 1. As we know, traditonal BIOS not only do some initialization work, but also put some data about the hardware in somewhere.BIOS even offer some routine such as intx( I know that In linux souce file "setup.s",int10, int13and int15 are used),but linuxbios doesn't offer. my question is: what is the mininal need of linux kernel's starting? what data does It need in detail? where does the data need to be placed in detail? what routine does linux kernel need for it's starting ? how does linuxbios offer these data and routines? 2. the second question is about PCI. I found that in linuxbios, some PCI initialization work is done.as we know ,in linux kernel, the same work was be done.Some linuxbios PCI initialization code is even the same with linux kernel. my question is: if the initialization in linuxbios is necessary? 3. my third question is about etherboot. I get a ide-patch of etherboot, and I succefully boot my system via IDE .I have read the code for a long time,but still have no idea about it. I found it seems does not do the same as setup.s,the kernel loader of traditional linux.who can explain it to me? I know there are some clever and experienced man in this site.I am very interested in this topic and admire all the man with good skills.I am looking forward to some help. best regards! yours HaimingWang

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question about option parameter
by Terry B. Chen 19 Feb '03

19 Feb '03

Hi all: Because the payload for normal image is too big, so I have to make one 1MB Linuxbios rom. Then I change the option ROM_SIZE=1048576 but I get a rom of 1,343,488. someone can help me?

1 0

via epia, pchips 787cl+
by Alexander Amelkin 19 Feb '03

19 Feb '03

Hello! The linuxbios status comments for via epia say "etherboot" only. Does that mean that epia won't be able to boot from a local ide hard drive? Are there any plans to implement the support for lilo/whatever booting from the hard drive on epia? Another question is about the pcchips 787cl+ 3.0 board. It's sis630e + it8705. I didn't find sis630e in the list of supported devices, but I found some discussion on how to enable or disable something on that chipset. That's confusing. Is sis630e supported, or is it not? With best regards, Alexander mailto:spirit@reactor.ru

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weighing in
by steven james 19 Feb '03

19 Feb '03

Greetings, Thinking about initialization where one device's init is required to make others show up: In the cases I have seen, any devices that require another device's setup, the new device either has a higher device or function number, or it is on a subordinate bus. The mose common case is the superIO devices which require both southbridge and PnP setup. Perhaps the best thing is a provision for a function call upon scanning a device. That function would init it far enough to reveal anything behind it and no further. It could then either scan any subordinate busses and dependant devices, or just return and let the scan that found it continue to higher dev/fn numbers. G'day, sjames -- -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office 404.577.7747 fax 404.577.7743 -----------------------------------------------------------------------

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