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Re:Re: How to initialize USB controller in LinuxBios?
by riskin＠263.net 23 Feb '03

23 Feb '03

----- Original Message ----- From: "ollie lho" <ollie(a)sis.com.tw> To: <riskin(a)263.net> Cc: <aip(a)cwlinux.com>,<jerj(a)coplanar.net>,"LinuxBIOS Mailing List" <linuxbios(a)clustermatic.org>,"Ronald G Minnich" <rminnich(a)lanl.gov> Sent: 2003-02-21 20:29:46 Subject: Re: How to initialize USB controller in LinuxBios? >On Fri, 2003-02-21 at 10:26, riskin(a)263.net wrote: >Do you really have any idea about USB controller ?? USB controller >does not require IP address space, it uses MMIO address space which >is called non-prefetchable memory in PCI spec. The controller does >not need any special init stuff. I don't think USB is supported by >2.2.x kernel neither. Why do you insist using 2.2.x kernel ? > >-- >ollie lho <ollie(a)sis.com.tw> I don't want to use 2.2.x kernel,but for some reasons, I must use the version. I don't know about USB controller indeed. But why do I see "I/O" addresses in standard bios environment on other boxes(not sis630e chipset),instead of non-prefetchable memory? In addition,there are patches supporting USB in 2.2.x kernel.I have successfully tried it on standard bios environment with 2.2.x kernel. Thanks, riskin ========================== 263电子邮件－信赖邮自专业

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gx1 ram size error
by zhu shi song 23 Feb '03

23 Feb '03

now i can boot my ec3 mainboard, but linuxbios can only find 32M ram, but I have 256M RAM. do you meet such problem? ec3 mainboard specification: processor: on-board NS GX1 233MHZ(fanless) chipset: NS CS5530A System Memory: one SDRAM DIMM BIOS: 2Mbit Flash BIOS solid state disk: support diskonchip 2000 --------------------------------- Do you Yahoo!? Yahoo! Tax Center - forms, calculators, tips, and more

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2 questions.. 1. laptops and linuxbios, 2. bios-savior for laptops?
by Nicholas Mistry 21 Feb '03

21 Feb '03

ok, sorry for the dual post, but they are somewhat related. 1. I havent really put much thought to using linuxbios on a laptop, but a recent post has planted a bug in my brain to try and get it to work on some of the older laptops i have laying around. How many people have tried to get linux bios on their laptops, and how well does it work. this issue now prompts this quesion: 2. What type of "bios savior" options are there for laptops? or is that just a pipe dream at this point? -N

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help
by xu xuning 21 Feb '03

21 Feb '03

Hello everyone: I have used Kernel-2.4.19_CWLINUX_4 from http://www.cwlinux.com/downloads/linuxbios-sdk/kernel/2.4.19/ but failed! my machine is winfast6300 MA Pro (doc md2800-d08 on i686), and through the console ( i use hypertrm.exe from windows on another machine),the information is following: ###################################################### LinuxBIOS-1.0.0 Mon Jan 20 15:34:48 EST 2003 starting... Copying LinuxBIOS to ram. LinuxBIOS-1.0.0 Mon Jan 20 15:34:48 EST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 handle_superio start, s 0000ce80 nsuperio 1 s->super 0000e1f8 handle_superio Pass 0, check #0, s 0000ce80 s->super 0000e1f8 handle_superio: Pass 0, Superio SiS 950 handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 0, done #0 handle_superio done Scanning PCI bus...PCI: PCI: 00:00.0 [1039/0630] PCI: 00:00.1 [1039/5513] PCI: 00:01.0 [1039/0008] PCI: 00:01.1 [1039/0900] PCI: 00:01.2 [1039/7001] PCI: 00:01.3 [1039/7001] PCI: 00:01.4 [1039/7018] PCI: 00:01.6 [1039/7013] PCI: 00:02.0 [1039/0001] PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1039/6300] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done totalram:56M Initializing CPU #0 Updating microcode microcode_info: sig = 0x00000683 pf=0x00000010 rev = 0x00000000 Enabling cache... Setting fixed MTRRs(0-88 Setting fixed MTRRs(0-16) type:HB DONE fixed MTRRs Setting variable MTRR 0 , base: 0MB,range: 32MB,type HB Setting variable MTRR 1 , base: 32MB,range: 16MB, type HB Setting variable MTRR 2, base: 48MB, range: 8MB, type HB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index :2 Vendor ID :GenuineIntel Processor Type :0x00 Processor Family :0x06 Processor Model :0x08 Processor Mask Processor Stepping:0x03 Feature flags :0x0383fbff Cache/TLB descriptor values: 1 reads required Desc 0x01 : Instr TLB:4KB pages, 4-way set assoc,32 entries Desc 0x02 : Instr TLB:4MB pages,fully assoc,2 entries Desc 0x03 : Data TLB: 4KB pages,4-way set assoc, 64 entries Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x41 : L2 Unified cache: 128K bytes, 4-way set assoc, 32 byte line size Desc 0x08 : Inst cache: 16K bytes,4-way set assoc,32 byte line size Desc 0x04 : Data TLB:4MB pages,4-way set assoc,8 entries Desc 0x0c : Data cache:16K bytes,2-way or 4-way or 4-way set assoc,32 byte line size MTRR check Fixed MTRRs: Enabled Variable MTRRs: Enabled Configuring L2 cache...CPU signature of 680 so no L2 cache configuration Enable Cache done. Disabling local apic...done CPU #0 Initialized Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 10 <- [0x8000000 - 0xfbffffff] mem PCI: 00:00.1 10 <- [0x00002c90 - 0x00002c93] io PCI: 00:00.1 14 <- [0x00002ca0 - 0x00002ca3] io PCI: 00:00.1 18 <- [0x00002cb0 - 0x00002cb3] io PCI: 00:00.1 1c <- [0x00002cc0 - 0x00002cc3] io PCI: 00:00.1 20 <- [0x00002c80 - 0x00002c83] io PCI: 00:00.1 10 <- [0x00002000 - 0x000020ff] io PCI: 00:01.1 14 <- [0xfc100000 - 0xfc100fff] mem PCI: 00:01.2 10 <- [0xfc101000 - 0xfc101fff] mem PCI: 00:01.3 10 <- [0xfc102000 - 0xfc102fff] mem PCI: 00:01.4 10 <- [0x00002400 - 0x000024ff] io PCI: 00:01.4 14 <- [0xfc103000 - 0 PCI: 00:01.6 10 <- [0x00002800 - 0x000028ff] io PCI: 00:01.6 14 <- [0x00002c00 - 0x00002c7f] io PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 io PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 prefmem PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io Allocating VGA resource done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 0 PCI: 00:00.1 cmd <- 01 PCI: 00:01.0 cmd <- 0c PCI: 00:01.1 cmd <- 03 PCI: 00:01.2 cmd <- 02 PCI: 00:01.3 cmd <- 02 PCI: 00:01.4 cmd <- 03 PCI: 00:01.6 cmd <- 01 PCI: 00:02.0 cmd <- 27 PCI: 01:00.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized Enabled in SIS 503 regs 0x40 and 0x45 Now try to turn off shadow device for SiS 630 is 0x127ec Shadow memory disabled in SiS 630 handle_superio start, s 0000ce80 nsuperio 1 s->super 0000e1f8 handle_superio Pass 1, check #0, s 0000ce80 s->super 0000e1f8 handle_superio: Pass 1, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 1, done #0 handle_superio done Winfast 6300 (and similar)...Entering the initregs process Southbridge fixup done for SIS 503 handle_superio start, s 0000ce80 nsuperio 1 s->super 0000e1f8 handle_superio Pass 2, check #0, s 0000ce80 s->super 0000e1f8 handle_superio: Pass 2, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call finishup handle_superio Pass 2, done #0 handle_superio done Checking IRQ routing tables.../opt/cwlinux/freebios/src/arch/i386/lib/pirq_routing.c: 23: check_pirq_routiing_table() - irq_routing_table located at : 0x0000a94 done. Copying IRQ routing tables to 0xf0000...done. Wrote linuxbios table at : 00000500 - 0000067c checksum 7c69 Jumping to linuxbiosmain()... Welcome to start32, the open sourced starter. This space will eventually hold more diagnostic information. Jamuary 2000 , James Hendricks, Dale Webster,and Ron Version 0.1 init_bytes Gunzip setup gunzip_setup output data is 0x00100000 Gunzipping boot code 42:fill_inbuf() - ram buffer:-0x0001afe4 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x00010000 block_count:0 inbuf[0] is 0x1f flush 0x00100000 count 0x00008000 flush 0x00108000 count 0x00008000 flush 0x00110000 count 0x00008000 flush 0x00118000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x00020000 block_count:1 inbuf[0] is 0x3b flush 0x00120000 count 0x00008000 flush 0x00128000 co flush 0x00130000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x00030000 block_count:2 inbuf[0] is 0xf1 flush 0x00138000 count 0x00008000 flush 0x00140000 count 0x00008000 flush 0x00148000 count 0x00008000 flush 0x00150000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x00040000 block_count:3 inbuf[0] is 0xe2 flush 0x00158000 count 0x00008000 flush 0x00160000 count 0x00008000 flush 0x00168000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x0 inbuf[0] is 0x4d flush 0x00170000 count 0x00008000 flush 0x00178000 count 0x00008000 flush 0x00180000 count 0x00008000 flush 0x00188000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x00060000 block_count:5 inbuf[0] is 0x7e flush 0x00190000 count 0x00008000 flush 0x00198000 count 0x00008000 flush 0x001a0000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x00070000 block_count:6 inbuf[0] is 0x5d flush 0x001a8000 count 0x00008000 flush 0x001b0000 count 0x00008000 flush 0x001b8000 count 0x00008000 flush 0x001c0000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x00080000 block_count:7 inbuf[0] is 0x2d flush 0x001c8000 count 0x00008000 flush 0x001d0000 count 0x00008000 flush 0x001d8000 count 0x00008000 flush 0x001e0000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x00090000 block_count:8 inbuf[0] is 0x6b flush 0x001e8000 count 0x00008000 flush 0x001f0000 count 0x00008000 flush 0x001f8000 count 0x00008000 flush 0x00200000 count 0x00008000 flush 0x00208000 count 0x00008000 flush 0x00210000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x000a0000 block_count:9 inbuf[0] is 0x6e flush 0x00218000 count 0x00008000 flush 0x00220000 count 0x00008000 flush 0x00228000 count 0x00008000 flush 0x00230000 count 0x00008000 done memcpy_from_doc_mil 52:fill_inbuf() - nvram:0x000b0000 block_count:10 inbuf[0] is 0x32 flush 0x00238000 count 0x00008000 flush 0x00240000 count 0x00008000 flush 0x00248000 count 0x00008000 flush 0x00250000 count 0x00003de0 <1001> fini_bytes command line - [root=/dev/nftla console=ttyS0,115200 console=/dev/tty5 CONSOLE=/ dev/tty5 video=sisfb:640x480-8@60,font:VGA8x16] Jumping to boot code ################################################################## On my LinuxBIOS machine ,cann't get into the system and only a picture ! So can you tell me what's wrong with me and how to do next? thanks a lot! _________________________________________________________________ 免费下载 MSN Explorer: http://explorer.msn.com/lccn/

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Information
by Xavier Pegenaute 21 Feb '03

21 Feb '03

Hi, i'm new in the list and i'd like know more things about put Kernel Linux in flashrom. 1) i'd like know a right map of a flashrom.At the moment i know that Bios code start at 0xf000h in 16 bits mode, in 0xc000h, there is VGA bios. 2) i want test your work with simulator like bochs, is there some document to try it ..? Yes, i well-read the information in your web. And all aditional docs will be a good thing. Thanks. Xavi.

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Intel IDF - EFI to replace BIOS
by Bari Ari 21 Feb '03

21 Feb '03

Looks like Intel is predicting EFI to replace BIOS soon from the presentation at the IDF this week. http://news.zdnet.co.uk/story/0,,t269-s2130826,00.html http://slashdot.org/article.pl?sid=03/02/20/189208 http://www.anandtech.com/showdoc.html?i=1791&p=2 http://www.intel.com/technology/efi/index.htm Bari

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RE: how to choice fallback or normal image?
by Terry B. Chen 21 Feb '03

21 Feb '03

I read the code in cmos_failover.inc But I don’t understand that RTC_BOOT_BYTE bit 1 gets the value from bit 0, the program clear bit 0 every time. But When to set the bit0 to 1, it will make the code jump to normal image next time? I search 0x70(cmos index) in all but I cant find when set bit 0 to 1? -----Original Message----- From: steven james [mailto:pyro@linuxlabs.com] Sent: 2003年2月20日 23:27 To: Terry B. Chen Cc: linuxbios(a)clustermatic.org Subject: Re: how to choice fallback or normal image? Greetings, Several conditions need to exist for the primary image to be used. The code looks at the RTC register to check for indication of power failure (either battery dead, or clear CMOS jumper set), then the CMOS checksum is checked. If both tests show that CMOS is valid, then check the RTC_BOOT_BYTE. First, bit 0 is moved to bit 1 and bit 0 is cleared. Then, if bit 1 is set, call the primary (normal image), That is done so that if the boot fails for some reason, it will choose the fallback image next time. It is also possible to cause a fallback boot by setting the clear CMOS jumper. The RTC_BOOT_BYTE is not included in the checksum since it will be changed wi8th every boot. Note that on some boards, the CMOS checksum is skipped. G'day, sjames The RTC_BOOT_BYTE On Thu, 20 Feb 2003, Terry B. Chen wrote: > Dear all: > I was puzzled by the fallback and normal image in s2722 > (e7500), I am sorry to ask so simple question. When shall we use the > fallback image and when shall we use the normal image? How you control > which to run? > The register DRC (7c) bit 29(Init complete) seem not to be set > after memory initialization complete. am I right? > Thank you! > -- -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office 404.577.7747 fax 404.577.7743 -----------------------------------------------------------------------

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How to initialize USB controller in LinuxBios?
by riskin＠263.net 20 Feb '03

20 Feb '03

Hi,ollie, My kernel is "2.2.14",so I need to initialize USB controller in LinuxBios. But,I don't know how to correctly initialize USB controller in LinuxBios on the sis630e chipset. I have checked the USB pci config space on the sis630e chipset, so I assigned "I/0" addresses "0xd001<<12" and "0xd8001<<12". And,the function number of the tow USB controller is 2 and 3. So,I modified LinuxBios like following: void pci_usb_enable(unsigned bus, unsigned slot, unsigned int irq) { unsigned functNum; struct pci_dev *pdev; unsigned char line; unsigned char readback; u32 io[2]={0xd001<<12,0xd801<<12}; for (functNum = 2; functNum < 4; functNum++) { pdev = pci_find_slot(bus, (slot << 3) + functNum); if (pdev) { pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &line); printk_debug("USB PIN: %d\n",line); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, \ io[functNum-2]); pci_write_config_byte(pdev, PCI_COMMAND, \ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); if ((line >= 1) && (line <= 4)) { printk_debug("Assigning usb IRQ %d to %d:%x.%d\n", \ irq, bus, slot, functNum); pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,\ irq); pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, \ &readback); printk_debug(" Readback = %d\n", readback); } } } } ... pci_usb_enable(0,1,0xa); ... After done this,I looked up /proc/pci: PCI devices found: Bus 0, device 0, function 0: Host bridge: Silicon Integrated Systems Unknown device (rev 33). Vendor id=1039. Device id=630. Medium devsel. Master Capable. Latency=64. Non-prefetchable 32 bit memory at 0xf8000000 [0xf8000000]. Bus 0, device 0, function 1: IDE interface: Silicon Integrated Systems 85C5513 (rev 208). Fast devsel. IRQ 14. Master Capable. Latency=16. I/O at 0x2c00 [0x2c01]. Bus 0, device 1, function 0: ISA bridge: Silicon Integrated Systems 85C503 (rev 0). Medium devsel. Master Capable. No bursts. Bus 0, device 1, function 1: Ethernet controller: Silicon Integrated Systems Unknown device (rev 131). Vendor id=1039. Device id=900. Medium devsel. Fast back-to-back capable. IRQ 9. Master Capable. Latency=64. Min Gnt=52.Max Lat=11. I/O at 0xb000 [0xb001]. Non-prefetchable 32 bit memory at 0xfc108000 [0xfc108000]. Bus 0, device 1, function 2: USB Controller: Silicon Integrated Systems 7001 USB (rev 7). Medium devsel. Fast back-to-back capable. IRQ 10. Master Capable. Latency=64. Max Lat=80. Non-prefetchable 32 bit memory at 0xd001000 [0xd001000]. Bus 0, device 1, function 3: USB Controller: Silicon Integrated Systems 7001 USB (rev 7). Medium devsel. Fast back-to-back capable. IRQ 10. Master Capable. Latency=64. Max Lat=80. Non-prefetchable 32 bit memory at 0xd801000 [0xd801000]. Bus 0, device 2, function 0: PCI bridge: Silicon Integrated Systems 5591/5592 AGP (rev 0). Fast devsel. Master Capable. No bursts. Min Gnt=8. Bus 0, device 9, function 0: Bridge: Texas Instruments Unknown device (rev 0). Vendor id=104c. Device id=ac60. Medium devsel. IRQ 5. Non-prefetchable 32 bit memory at 0xfc10b000 [0xfc10b000]. Non-prefetchable 32 bit memory at 0xfc100000 [0xfc100000]. Non-prefetchable 32 bit memory at 0xfc10c000 [0xfc10c000]. Bus 0, device 11, function 0: Ethernet controller: Realtek 8139 (rev 16). Medium devsel. Fast back-to-back capable. IRQ 10. Master Capable. Latency=64. Min Gnt=32.Max Lat=64. I/O at 0x2400 [0x2401]. Non-prefetchable 32 bit memory at 0xfc10d000 [0xfc10d000]. Bus 0, device 13, function 0: Ethernet controller: Realtek 8139 (rev 16). Medium devsel. Fast back-to-back capable. IRQ 9. Master Capable. Latency=64. Min Gnt=32.Max Lat=64. I/O at 0x2800 [0x2801]. Non-prefetchable 32 bit memory at 0xfc10e000 [0xfc10e000]. Bus 1, device 0, function 0: VGA compatible controller: Silicon Integrated Systems Unknown device (rev 33). Vendor id=1039. Device id=6300. Medium devsel. Fast back-to-back capable. BIST capable. Prefetchable 32 bit memory at 0xf0000000 [0xf0000008]. Non-prefetchable 32 bit memory at 0xfc000000 [0xfc000000]. I/O at 0x1000 [0x1001]. I didn't find The "I/O" addresses of USB controller. So,is there other things need to be done to initialize USB controller correctly? Could you help me? Thanks, riskin ========================== 263电子邮件－信赖邮自专业

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how to choice fallback or normal image?
by Terry B. Chen 20 Feb '03

20 Feb '03

Dear all: I was puzzled by the fallback and normal image in s2722 (e7500), I am sorry to ask so simple question. When shall we use the fallback image and when shall we use the normal image? How you control which to run? The register DRC (7c) bit 29(Init complete) seem not to be set after memory initialization complete. am I right? Thank you!

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ALI M1429L 386/486 mem ctlr datasheet - anyone have it?
by Jeremy Jackson 20 Feb '03

20 Feb '03

I'm looking at bits and pieces of a TI/Acer Extensa 455T laptop, and I would like to try LinuxBIOS for it if I can get the datasheet. I wrote ALI, but I'm not getting my hopes up. -- Jeremy Jackson <jerj(a)coplanar.net>

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