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problem with rom
by Serafino Sorrenti 09 May '03

09 May '03

This is my pcchips.config, in i have set video_console=0 but when i probe to make the file i have this error.\ gcc ... -o superio_sis_950.o /home/fino/src/superio/sis/950/superio.c /home/fino/src/superio/sis/950/superio.c:2: warning: `rcsid' defined but not used gcc ... -o nsuperio.o nsuperio.c gcc ... -o mainboard.o /home/fino/src/mainboard/pcchips/m810lmr/mainboard.c gcc ... -o irq_tables.o /home/fino/src/mainboard/pcchips/m810lmr/irq_tables.c gcc ... -o cpuid.o /home/fino/src/cpu/p5/cpuid.c /home/fino/src/cpu/p5/cpuid.c:3: warning: `rcsid' defined but not used gcc ... -o delay_tsc.o /home/fino/src/cpu/p5/delay_tsc.c /home/fino/src/cpu/p5/delay_tsc.c: In function `calibrate_tsc': /home/fino/src/cpu/p5/delay_tsc.c:102: warning: unused variable `allones' gcc ... -o microcode.o /home/fino/src/cpu/p6/microcode.c /home/fino/src/cpu/p6/microcode.c:7: warning: `rcsid' defined but not used gcc ... -o mtrr.o /home/fino/src/cpu/p6/mtrr.c /home/fino/src/cpu/p6/mtrr.c: In function `set_var_mtrr': /home/fino/src/cpu/p6/mtrr.c:132: warning: unused variable `tmp' /home/fino/src/cpu/p6/mtrr.c: At top level: /home/fino/src/cpu/p6/mtrr.c:29: warning: `rcsid' defined but not used gcc ... -o l2_cache.o /home/fino/src/cpu/p6/l2_cache.c /home/fino/src/cpu/p6/l2_cache.c:33: warning: `rcsid' defined but not used gcc ... -o cpufixup.o /home/fino/src/cpu/k7/cpufixup.c /home/fino/src/cpu/k7/cpufixup.c:8:1: warning: "TOP_MEM" redefined In file included from /home/fino/src/cpu/k7/cpufixup.c:6: /home/fino/src/include/cpu/k7/mtrr.h:38:1: warning: this is the location of the previous definition /home/fino/src/cpu/k7/cpufixup.c:9:1: warning: "TOP_MEM2" redefined /home/fino/src/include/cpu/k7/mtrr.h:39:1: warning: this is the location of the previous definition rm -f linuxbios.a ar cr linuxbios.a linuxbiosmain.o linuxpci.o newpci.o clog2.o printk.o serial_subr.o subr.o vsprintf.o memset.o memcpy.o memcmp.o malloc.o do_inflate.o delay.o compute_ip_checksum.o version.o keyboard.o mc146818rtc.o isa-dma.o ide.o boot.o linuxbios_table.o i386_subr.o params.o hardwaremain.o pirq_routing.o c_start.o southbridge.o northbridge.o superio_sis_950.o nsuperio.o mainboard.o irq_tables.o keyboard.o cpuid.o delay_tsc.o microcode.o mtrr.o l2_cache.o cpufixup.o cpufixup.o gcc -nostdlib -r -o linuxbios_c.o c_start.o docmil_fill_inbuf.o ide_fill_inbuf.o linuxbios.a /usr/lib/gcc-lib/i386-linux/3.2.3/libgcc.a perl -e 'foreach $var (split(" ", $ENV{VARIABLES})) { if ($ENV{$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$/) { print "$var = $ENV{$var};\n"; }}' > ldoptions gcc -nostdlib -nostartfiles -static -o linuxbios_c -T /home/fino/src/config/linuxbios_c.ld linuxbios_c.o linuxbios_c.o(.text+0x51a): In function `displayinit': : undefined reference to `video_init' linuxbios_c.o(.text+0x52e): In function `__display_tx_byte': : undefined reference to `video_tx_byte' linuxbios_c.o(.text+0x5ec1): In function `set_display': : undefined reference to `video_col' linuxbios_c.o(.text+0x5ec9): In function `set_display': : undefined reference to `video_line' collect2: ld returned 1 exit status make: *** [linuxbios_c] Error 1 samyr:/home/fino/freebios/util/config/pcchips# Tnx Serafino

6 22

jmp INSTRUCTION IN boot.c fails and resets again , what couldbethe reason.
by Russell Gower 09 May '03

09 May '03

> I couldn't get the ram init to work at all with any of my DIMMS on a Epia > 5000. > So I hacked my build to use the generic SPD routines for ram init, It works > a treat but i'm way out of sync with CVS now! and i don't know how to > produce the right sort of diff ( don't laugh) <g> If you tell me what > parameters to use i'll have a go if anyone is intrested. > > > Russell > > Sorry if this appears twice, I'll remember to send it from the right Email address one day!

2 1

PLCC paged flash?
by Andre Dias 09 May '03

09 May '03

Hello Folks, Is there any PLCC fkash chip that has paged memory like DOC, so we could use in the new motherboards?

4 3

Re: jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by Richard Smith 09 May '03

09 May '03

>>RAMTEST is usually good enough to catch errors so bad you >>can't get past the BIOS without fixing them. > > Agreed. But the part in question has proved in the past to be unusually > difficult (for me anyway) to get working. For this case I think memtest86 > is appropriate. I guess I don't understand how memtest86 is going to load and run if he can't sucessfully jump to a loaded elf image. -- Richard A. Smith rsmith(a)bitworks.com -- Richard A. Smith rsmith(a)bitworks.com

2 1

problem on boot
by Serafino Sorrenti 09 May '03

09 May '03

After make the linuxbios rom i have this problem, the machine is look on boot, and this is the log of the serial port. PCI devices initialized Enabled in SIS 503 regs 0x40 and 0x45 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 1, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 1, done #0 handle_superio done PCCHIPS M810LMR (and similar)...Entering the initregs process Southbridge fixup done for SIS 503 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 2, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call finishup handle_superio Pass 2, done #0 handle_superio done Copying IRQ routing tables to 0xf0000...done. Wrote linuxbios table at: 00000500 - 0000066c checksum ba14 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 (cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: 0x0000000000008789 Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417 Jumping to boot code ROM segment 0x0000 length 0x0000 reloc 0x0000 Etherboot 5.0.6 (GPL) ELF for [SIS900] Boot from (N)etwork or from (L)ocal? clocks_per_tick = 784576 N I am now initializing the ide system init_drive sectors_per_track = [0], num_heads = [0],num_cylinders=[0], num_sectors = [0] CHS mode... Boot: (hd0,0)/kernel The machine is stalled with this messagges. Tnx Serafino

3 2

problem on boot
by Serafino Sorrenti 09 May '03

09 May '03

this is the full log of minicom Welcome to minicom 2.00.0 OPTIONS: History Buffer, F-key Macros, Search History Buffer, I18n Compiled on Apr 30 2003, 17:04:09. Press CTRL-A Z for help on special keys 0 LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 starting... Copying LinuxBIOS to ram. LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 booting... Finding PCI configuration type. PCI: Using configuration type 1 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 0, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 0, Superio SiS 950 handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 0, done #0 handle_superio done Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1039/0730] PCI: 00:00.1 [1039/5513] PCI: 00:01.0 [1039/0008] PCI: 00:01.1 [1039/0900] PCI: 00:01.2 [1039/7001] PCI: 00:01.3 [1039/7001] PCI: 00:01.4 [1039/7018] PCI: 00:01.6 [1039/7013] PCI: 00:02.0 [1039/0001] PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1039/6300] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done totalram: 1016M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 512MB, type WB Setting variable MTRR 1, base: 512MB, range: 256MB, type WB Setting variable MTRR 2, base: 768MB, range: 128MB, type WB Setting variable MTRR 3, base: 896MB, range: 64MB, type WB Setting variable MTRR 4, base: 960MB, range: 32MB, type WB Setting variable MTRR 5, base: 992MB, range: 16MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : AuthenticAMD Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x08 Processor Mask : 0x00 Processor Stepping : 0x00 Feature flags : 0x0183f9ff MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] mem PCI: 00:00.1 10 <- [0x00002c90 - 0x00002c93] io PCI: 00:00.1 14 <- [0x00002ca0 - 0x00002ca3] io PCI: 00:00.1 18 <- [0x00002cb0 - 0x00002cb3] io PCI: 00:00.1 1c <- [0x00002cc0 - 0x00002cc3] io PCI: 00:00.1 20 <- [0x00002c80 - 0x00002c8f] io PCI: 00:01.1 10 <- [0x00002000 - 0x000020ff] io PCI: 00:01.1 14 <- [0xfc100000 - 0xfc100fff] mem PCI: 00:01.2 10 <- [0xfc101000 - 0xfc101fff] mem PCI: 00:01.3 10 <- [0xfc102000 - 0xfc102fff] mem PCI: 00:01.4 10 <- [0x00002400 - 0x000024ff] io PCI: 00:01.4 14 <- [0xfc103000 - 0xfc103fff] mem PCI: 00:01.6 10 <- [0x00002800 - 0x000028ff] io PCI: 00:01.6 14 <- [0x00002c00 - 0x00002c7f] io PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 ??????io PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 ??????prefmem PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 ??????mem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io Allocating VGA resource done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 07 PCI: 00:00.1 cmd <- 01 PCI: 00:01.0 cmd <- 0c PCI: 00:01.1 cmd <- 03 PCI: 00:01.2 cmd <- 02 PCI: 00:01.3 cmd <- 02 PCI: 00:01.4 cmd <- 03 PCI: 00:01.6 cmd <- 01 PCI: 00:02.0 cmd <- 27 PCI: 01:00.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized Enabled in SIS 503 regs 0x40 and 0x45 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 1, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 1, done #0 handle_superio done PCCHIPS M810LMR (and similar)...Entering the initregs process Southbridge fixup done for SIS 503 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 2, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call finishup handle_superio Pass 2, done #0 handle_superio done Copying IRQ routing tables to 0xf0000...done. Wrote linuxbios table at: 00000500 - 0000066c checksum ba14 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 (cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: 0x0000000000008789 Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417 Jumping to boot code ROM segment 0x0000 length 0x0000 reloc 0x0000 Etherboot 5.0.6 (GPL) ELF for [SIS900] Boot from (N)etwork or from (L)ocal? clocks_per_tick = 784463 N I am now initializing the ide system init_drive sectors_per_track = [0], num_heads = [0],num_cylinders=[0], num_sectors = [0] CHS mode... Boot: (hd0,0)/kernel this is the output of the serial boot n boot. Tnx Serafino

1 0

810E northbridge initialization problem
by Shubhangi Jadhav 09 May '03

09 May '03

Hi, Here's the northdump and the lspci dump for the 810E northbridge. The only difference I see is in the PCISTS (PCI status) register setting (0x06-07h). Does this affect the ram initialization. In raminit.inc I'm setting the value of this register to 0x2080, but cannot see it being reflected in the northdump output. Could this cause problems in ram initialization? Also I have this small program which sets the value of the PCISTS register, however it modified the register value only the first time and never after that. Any pointers on what could be the reason? **************************northdump output :******************************* 00: 86 80 24 71 06 00 80 00 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 24 71 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 28 53 0a 38 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: c6 78 18 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 eb fb 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 **************************northdump output :******************************* **************************lspci output :************************************* 00:00.0 Host bridge: Intel Corporation 82810E GMCH [Graphics Memory Controller Hub] (rev 03) 00: 86 80 24 71 06 00 80 20 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 24 71 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 28 53 0a 38 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: c6 78 18 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 eb fb 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 **************************lspci output :************************************* Regards, Shubhangi

2 2

jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by Deepak Kotian 09 May '03

09 May '03

Hi, after putting some debug statements, it seems the LinuxBIOS resets after the jmp instruction is boot.c ( " jmp *%%eax\n\t" in jmp_to_elf_entry) fails. I am using ETHERBOOT payload with IDE support. Is it because the ram initialization is not proper or something, has anyone experienced this kind of problem. Any pointers, why it should fail over here. Here is the extract of the log ... ********* calling elf load... New segment addr 0x94000 size 0x8128 offset 0x60 filesize 0x38d4 (cleaned up) New segment addr 0x94000 size 0x8128 offset 0x60 filesize 0x38d4 Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000008128 filesz: 0x00 000000000038d4 Clearing Segment: addr: 0x00000000000978d4 memsz: 0x0000000000004854 Jumping to boot code at 0x94000 LinuxBIOS-1.0.0 Thu May 1 04:29:36 IST 2003 starting... Ram1 ********* Regards Deepak

5 10

Re: jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by dkotian3＠vsnl.net 08 May '03

08 May '03

I have enabled RAMTEST(ramtest.inc) in the LinuxBIOS, it seems to be running at a very slow pace.Hope it finishes off by today. *****Extract***** dump northbridge: 00: 86 80 24 71 06 00 80 00 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 00 24 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 28 53 09 3c 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: c6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 eb fb 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 Done. Testing SDRAM : 80000a00-ffff0f30 SDRAM fill: 887e0000 *****Extract***** The number(887?????) increments at a very slow pace and has been more than an hour now. Moreover, I have 64MB ram, does the above range of test look OK. If has basically happened after changing some parameter in the North Bridge. I have run ramtest before as well without the changes. ****Extract Before ***** Testing SDRAM : 00000000-0009ffff SDRAM fill: 000000000001000000020000000300000004000000050000000600000007000000080000000900000009ffff SDRAM verify: 000000000001000000020000000300000004000000050000000600000007000000080000000900000009ffff Done. ****Extract Before ***** But in this case also, it used to reset... I hope, this what is expected in the Successful Output of Ramtest. Any pointers on this one. Regards Deepak

3 3

Status freebios2...
by ebiederman＠lnxi.com 08 May '03

08 May '03

I am busily working on getting the switching from fallback to normal mode working in LinuxBIOS. To that end I have just implemented and committed structure and typedef support in LinuxBIOS. I realized the other day that to remove assembly code I would need to be able to call rdmsr && wrmsr from code compiled with romcc. rdmsr returns 2 values so I needed structure support. And typedef support was simple to implement and so I fixed it while I was in there. Hopefully I can now make some more progress. Eric

1 0

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coreboot