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Documentation
by Xavier Pegenaute 05 May '03

05 May '03

Hello, i'm doing documentation about the code of LinuxBios with ADLO for my thesis, and i thought that may be you can helpme in things that are usefull to know for understand the code of LinuxBios. Of course after the document can be for linuxbios. I started by a mail of Greg Watson that explain how is linked crt0.S and linuxbios, after this i started to explain the main things of hardwaremain.c that jump to the elfboot and finally elfboot to kernel. Any one thing that is usefull to explain something else ? Another thing that is a little confused in me .., the true point of start code, in some info say that is in 0xf0000, but in the compilation of ms7308e i see that is in: linuxbios.map:00080004 T _start i supose that then it depends of the motherboard ... At the moment it's all. Thanks for all. Xavi.

5 4

make rom problem!
by Serafino Sorrenti 05 May '03

05 May '03

# This will make a target directory of ./pcchips target pcchips # PCCHIPS M810LMR mainboard mainboard pcchips/m810lmr # We are using a k7 cpu (???) cpu k7 # Set up udelay - needed option CONFIG_UDELAY_TSC=1 # This SHOULD enable the video console with messages about what's going on option VIDEO_CONSOLE=1 # Enable Serial Console for debugging option SERIAL_CONSOLE=1 # Sets the log level, from 9 to 1 (???) option DEFAULT_CONSOLE_LOGLEVEL=6 # More debug options option SERIAL_POST=1 # Enables ethernet (?) option ENABLE_MII=1 # use DOC MIL option USE_DOC_MIL=1 docipl northsouthbridge/sis/730/ipl.S # Use the internal VGA frame buffer device option HAVE_FRAMEBUFFER=1 # Sets the amount of framebuffer memory # 0x80 (2MB/4MB) # 0x90 (4MB/8MB) # 0xA0 (8MB/16MB) # 0xB0 (16MB/32MB) # 0xC0 (32MB/64MB) # 0xD0 (64MB/na) option SMA_SIZE=0xC0 # Enables IDE boot option BOOT_IDE=1 # Selects which IDE device should boot from, using the following table: # /dev/hda -> 0 # /dev/hdb -> 1 # /dev/hdc -> 2 # /dev/hdd -> 3 option IDE_BOOT_DRIVE=0 # Partition table size (should be left untouched?) option ONE_TRACK=32 # Need to "relocate the gdt" to use a standard flash part (???) biosbase 0xffff0000 # Path to your kernel (vmlinux) linux /usr/src/linux # Kernel command line parameters commandline root=/dev/hda1 console=ttyS0,115200 console=tty0 single This is my config file but when i done the make command in pcchips directory this is the error. gcc ... -o superio_sis_950.o /home/fino/src/superio/sis/950/superio.c /home/fino/src/superio/sis/950/superio.c:2: warning: `rcsid' defined but not used gcc ... -o nsuperio.o nsuperio.c gcc ... -o mainboard.o /home/fino/src/mainboard/pcchips/m810lmr/mainboard.c gcc ... -o irq_tables.o /home/fino/src/mainboard/pcchips/m810lmr/irq_tables.c gcc ... -o cpuid.o /home/fino/src/cpu/p5/cpuid.c /home/fino/src/cpu/p5/cpuid.c:3: warning: `rcsid' defined but not used gcc ... -o delay_tsc.o /home/fino/src/cpu/p5/delay_tsc.c /home/fino/src/cpu/p5/delay_tsc.c: In function `calibrate_tsc': /home/fino/src/cpu/p5/delay_tsc.c:102: warning: unused variable `allones' gcc ... -o microcode.o /home/fino/src/cpu/p6/microcode.c /home/fino/src/cpu/p6/microcode.c:7: warning: `rcsid' defined but not used gcc ... -o mtrr.o /home/fino/src/cpu/p6/mtrr.c /home/fino/src/cpu/p6/mtrr.c: In function `set_var_mtrr': /home/fino/src/cpu/p6/mtrr.c:132: warning: unused variable `tmp' /home/fino/src/cpu/p6/mtrr.c: At top level: /home/fino/src/cpu/p6/mtrr.c:29: warning: `rcsid' defined but not used gcc ... -o l2_cache.o /home/fino/src/cpu/p6/l2_cache.c /home/fino/src/cpu/p6/l2_cache.c:33: warning: `rcsid' defined but not used gcc ... -o cpufixup.o /home/fino/src/cpu/k7/cpufixup.c /home/fino/src/cpu/k7/cpufixup.c:8:1: warning: "TOP_MEM" redefined In file included from /home/fino/src/cpu/k7/cpufixup.c:6: /home/fino/src/include/cpu/k7/mtrr.h:38:1: warning: this is the location of the previous definition /home/fino/src/cpu/k7/cpufixup.c:9:1: warning: "TOP_MEM2" redefined /home/fino/src/include/cpu/k7/mtrr.h:39:1: warning: this is the location of the previous definition rm -f linuxbios.a ar cr linuxbios.a linuxbiosmain.o linuxpci.o newpci.o clog2.o printk.o serial_subr.o video_subr.o subr.o vsprintf.o memset.o memcpy.o memcmp.o malloc.o do_inflate.o delay.o compute_ip_checksum.o version.o keyboard.o mc146818rtc.o isa-dma.o vga_load_regs.o font_8x16.o vga_set_mode.o vga_load_pcx.o ide.o boot.o linuxbios_table.o i386_subr.o params.o hardwaremain.o pirq_routing.o c_start.o southbridge.o northbridge.o superio_sis_950.o nsuperio.o mainboard.o irq_tables.o keyboard.o cpuid.o delay_tsc.o microcode.o mtrr.o l2_cache.o cpufixup.o cpufixup.o gcc -nostdlib -r -o linuxbios_c.o c_start.o docmil_fill_inbuf.o ide_fill_inbuf.o linuxbios.a /usr/lib/gcc-lib/i386-linux/3.2.3/libgcc.a perl -e 'foreach $var (split(" ", $ENV{VARIABLES})) { if ($ENV{$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$/) { print "$var = $ENV{$var};\n"; }}' > ldoptions gcc -nostdlib -nostartfiles -static -o linuxbios_c -T /home/fino/src/config/linuxbios_c.ld linuxbios_c.o linuxbios_c.o(.text+0x45a7): In function `video_tx_byte': : undefined reference to `beep' collect2: ld returned 1 exit status make: *** [linuxbios_c] Error 1 samyr:/home/fino/freebios/util/config/pcchips# Tnx Serafino

3 2

jmp_to_elf_entry
by steven james 04 May '03

04 May '03

Greetings, Looks like I've trodden on an unused code path, and found a bug. In arch/i386/boot/boot.c: jmp_to_elf_entry, the idea is to copy all of the running code (linuxbios, or a baremetal payload) to a bounce buffer, jump into the copy there, copy the bounce buffer of the target elf into place, and call it. Upon return, the process is reversed, so that (in theory) jmp_to_elf_entry returns and further processing can happen. For some reason, the lines that subtract the adjustment from EAX, then jump to move execution back to the proper place was failing. I've patched it in the copy kept in util/baremetal/lib so that instead, it loads the eventual jmp target into ecx, then saves it away on the stack. I'm surely missing something here, but the original goes into space while the simple save off is working. I suppose that's just because we've never tried to return to LinuxBIOS from a payload before. The baremetal version also skips adjusting ESP since I'm moving the stack out of the way first. Ignore the // debugging stuff, that was just to see where things were going wrong (I'll be getting rid of that). Eric, since you wrote that part, I wanted to run this by you before making any changes in LinuxBIOS itself. G'day, sjames -- -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 2701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office 404.577.7747 fax 404.577.7743 -----------------------------------------------------------------------

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Experiences on Etherboot for IDE Compact flash and FLASHROMS
by dkotian3＠vsnl.net 03 May '03

03 May '03

Hi, Can some please list one's experiences on Etherboot to boot from IDE Compact flash over here. Basically, I have to put the etherboot payload and LinuxBIOS on 256K/512K FLASH ROMS and the Linux kernel image(2.4.18-3) and application on Compact Flash ide. Some kind of HOWTO/experience from many who have tried etherboot in this situation. If one can clearly give out the list or a link where one can find this document for this kind setup for etherboot. It would be great. Thanks and Regards Deepak Thanks and Regards Deepak

5 4

Bounce buffers and stack
by steven james 02 May '03

02 May '03

Greetings, I'm doing some work on payloads, chaining, and returning from an elf image and have run into an 'interesting' problem. Currently, when elfload sees that an image will overwrite LinuxBIOS, it moves everything (including the stack) up into high memory. So far, so good. However, in the case where it will not overwrite, it leaves things alone. The problem comes in where the payload then loads an image over the stack. So, for example, LinuxBIOS loads payload at 0x1000-0x4000, payload loads image at 0x5000-0x10000 and BOOM. The best bet is to have the first payload move the stack to the top of ram under the 4GB mark and somehow mark that memory as 'pre-boot reserved', meaning that bootloaders should leave it alone, but a final boot target such as Linux may use it after moving the stack. The idea is to allow for chaining by having each stage reserve it's chunk of memory (including bounce buffer) at top of ram-reserved, then move reserved down. jmp_to_elf_entry then just worries about IP and leaves ESP and EBP alone. Ideally, LinuxBIOS itself would create the stack high in the first place, but we are near the freeze, and the first stage payload can easily enough handle the ugliness and set a flag within baremetal to deal with this. Any thoughts? G'day, sjames -- -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 2701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office 404.577.7747 fax 404.577.7743 -----------------------------------------------------------------------

2 2

Sourceforge CVS
by Russell Gower 02 May '03

02 May '03

Has something change with sourceforges cvs since Feburary as i can't do an anonymous login any more. help :-) Russell ICQ 4186920

2 1

EEPROM not found
by Philippe CABANNES 02 May '03

02 May '03

>> I think the flash write enabled, I use this : >> setpci -s 0:11.0 40.b=54 >send me an lspci. Are you sure this is the right chip? I don´t know if it´s the right chip. Here is my lspci : 00:00.0 Host bridge: VIA Technologies, Inc.: Unknow device 3123 00:01.0 PCI bridge: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP] 00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. OHCI Compliant IEEE 1394 Host Controller (rev 80) 00:10.0 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80) 00:10.1 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80) 00:10.2 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80) 00:10.3 USB Controller: VIA Technologies, Inc.: Unknow device 3104(rev 80) 00:11.0 ISA bridge: VIA Technologies, Inc.: Unknow device 3177 00:11.1 IDE interface: VIA Technologies, Inc: Bus Master IDE (rev 06) 00:11.5 Multimedia audio controller: VIA Technologies, Inc. AC97 Audio Controller (rev 50) 00:12.0 Ethernet controller: VIA Technologies, Inc. Ethernet Controller (rev 74) 01:00.0 VGA Compatible controller: VIA Technologies, Inc.: Unknow device 3122 (rev 03) thanks. -------------------------------------------------- Oreka ! Nous sommes l'internet moins cher ! Surfez 25% moins cher avec http://www.oreka.com

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EEPROM not found
by Philippe CABANNES 02 May '03

02 May '03

2 1

flash utility
by Nhan NGO DINH 02 May '03

02 May '03

I've a Lex CV860A motherboard, which support has been recently added to LinuxBIOS. I can't find any flash program for that: the flash chip is an AMIC A290021TL-70. http://www.amictechnology.com/pdf/A290021.pdf Does mtd in Linux kernel support this kind of stuff? Thx. Nhan

1 0

PCMCIA Support
by tcc_linuxbios＠thinkthink.com 02 May '03

02 May '03

The reason I'm interested in linuxbios is that I'd like to create a self-contained (not remote booted) no-moving-parts system for ruggetized use. I'd be open to a better idea - but so far I'm thinking of putting an OpenBSD fs on a pcmcia ATA flash card and access it through one of those PCI<->pcmcia cards. This should make for a neat off-the-shelf system for firewalls, gateways, etc. Most bios's don't support pcmcia because most mb's don't have pcmcia hw... Therefore my linuxbios interest. Has anyone considered putting in PCMCIA support? A grep of sources and mail archive comes up blank, except for booting off of CF. CF would work but I suspect I have to buy a special (read expensive) mb that has CF support. Am I getting myself into a project? :) tom.c

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