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39780 discussions

28 Aug '03

Stephan, All about the duplicate code are for the multilink etc. I think after Eric and the code to enumerate the HT belongs to the CPU0. and make the static links to work in chip.h and ... it will be eliminated. (auto.c and pci_device.c and cpufixup.c may all need the static config processing code) Regards Yinghai Lu -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年8月28日 6:34 收件人: linuxbios(a)clustermatic.org 主题: Unified setup... Hi LYH, Ron and others, I've been looking at the recent changes that went into the tree, and I don't like the fact that a lot of code is duplicated. Is there some way to unify this? --- raminit.c 2003-08-28 14:43:39.000000000 +0200 +++ raminit.1.c 2003-08-28 06:42:50.000000000 +0200 [..] - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, This changes the link id where the southbridge is connected. We can get this information out of the configuration file since we are able to describe a map of all CHT components. On most machines the southbridge is probably connected to LDT0, but having two files for this one setting seems inappropriate. Ron, what is the easiest way of getting this information from the config file? LYH: To get this unified again, I added a resourcemap.c file to the s2885 directory that contains the resource map of the 2885. In auto.c this is used instead of the default. - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, same as above. - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x03000203, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x05040003, These change the bus numbers and read/write enables. How can we write these more general? +/* //BY LYH add IOMMU 64M APERTURE PCI_ADDR(0, 0x18, 3, 0x94), 0xffff8000, 0x00000f70, PCI_ADDR(0, 0x18, 3, 0x90), 0xffffff80, 0x00000002, PCI_ADDR(0, 0x18, 3, 0x98), 0x0000000f, 0x00068300, //BY LYH END +*/ I added a configuration variable ENABLE_IOMMU and set it to 1 for all existing boards except the s2885. It would be nice to have the size of the aperture also selectable via the configuration file, or even better during firmware run time. I am scared that changes for special motherboards will contaminate the source tree and make it hard for anyone to see what is actually going on. If this happens in a source tree for a special motherboard, it does not really matter, but I think it is a good goal to keep the generic code clean and generic and make it even more generic in the places where it's not sufficient. I'll look into coherent_ht.1.c and see if this can be done more general as well. I commited the attached patch. Please comment. Stefan -- Architecture Team SuSE Linux AG

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Unified setup...
by Stefan Reinauer 28 Aug '03

28 Aug '03

Hi LYH, Ron and others, I've been looking at the recent changes that went into the tree, and I don't like the fact that a lot of code is duplicated. Is there some way to unify this? --- raminit.c 2003-08-28 14:43:39.000000000 +0200 +++ raminit.1.c 2003-08-28 06:42:50.000000000 +0200 [..] - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, This changes the link id where the southbridge is connected. We can get this information out of the configuration file since we are able to describe a map of all CHT components. On most machines the southbridge is probably connected to LDT0, but having two files for this one setting seems inappropriate. Ron, what is the easiest way of getting this information from the config file? LYH: To get this unified again, I added a resourcemap.c file to the s2885 directory that contains the resource map of the 2885. In auto.c this is used instead of the default. - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, same as above. - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x03000203, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x05040003, These change the bus numbers and read/write enables. How can we write these more general? +/* //BY LYH add IOMMU 64M APERTURE PCI_ADDR(0, 0x18, 3, 0x94), 0xffff8000, 0x00000f70, PCI_ADDR(0, 0x18, 3, 0x90), 0xffffff80, 0x00000002, PCI_ADDR(0, 0x18, 3, 0x98), 0x0000000f, 0x00068300, //BY LYH END +*/ I added a configuration variable ENABLE_IOMMU and set it to 1 for all existing boards except the s2885. It would be nice to have the size of the aperture also selectable via the configuration file, or even better during firmware run time. I am scared that changes for special motherboards will contaminate the source tree and make it hard for anyone to see what is actually going on. If this happens in a source tree for a special motherboard, it does not really matter, but I think it is a good goal to keep the generic code clean and generic and make it even more generic in the places where it's not sufficient. I'll look into coherent_ht.1.c and see if this can be done more general as well. I commited the attached patch. Please comment. Stefan -- Architecture Team SuSE Linux AG

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Re: about VGA support in voyager2 board
by elife elife 28 Aug '03

28 Aug '03

Sorry for delayed reply. I will test it tomorrow. Thanks all! >From: ron minnich <rminnich(a)lanl.gov> >To: SONE Takeshi <ts1(a)cma.co.jp> >CC: elife elife <rimy2000(a)hotmail.com>, <linuxbios(a)clustermatic.org> >Subject: Re: about VGA support in voyager2 board >Date: Wed, 27 Aug 2003 08:14:47 -0600 (MDT) > >OK, would anyone like to test out my fixed vgabios with the devfn patch? > >I will look at moving the table to 0x1000. I actually think there was a >reason I kept all this on page 0, but that reason probably no longer >matters. > >ron > > _________________________________________________________________ 与联机的朋友进行交流，请使用 MSN Messenger: http://messenger.msn.com/cn

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LinuxBIOS problems with DoC
by Michel Belleau 28 Aug '03

28 Aug '03

Hi. VIA EPIA 800Mhz DIP2PLCC adapter DoC Millenium 8MB Slackware 9.0 on the HD I downloaded via CVS the latest version of Linuxbios and made my epia.config file. I can hotswap my BIOS chip with the DoC and Linux sees it when I load the modules. I can erase the chip and write whatever to it. I can build a romimage (256k) with Linuxbios but I don't have to guts yet to flash it on my original chip. *** Can I write it on the DoC? How? I don't seem to be able to build with the USE_DOC_MIL=1 option set in the config file. The make command always result in a failure, because "dd" doesn't have a valid argument for the size (it's a negative value). *** What are the values needed in the config file to prepare Linuxbios to be flashed on a DoC? I tried ROM_SIZE=838xxxx but the resulting "romimage" file is too big for the DoC. *** What are the steps to write the BIOS onto the DoC? Can I go step by step and check out what's wrong easily? Here's what I tried yesterday (by heart). modprobe doc2001 && modprobe docecc && modprobe docprobe (my DoC is found) erase /dev/mtd0 0 1024 (which erases the entire DoC, right?) dd if=docpil of=/dev/mtd0 (docipl is supposed to be at the first block, right?) dd if=docipl of=/dev/mtd0 seek=1 (docipl is at the second block too, right?) dd if=romimage.via-rhine of=/dev/mtd0 seek=2 (i TRIED by guess to put the romimage I built earlier right after the two docipl) reboot (shut off the computer beacuse it hangs at "Rebooting the system...") When I power it up, nothing comes up on my serial console, just like when I tried starting the board without a BIOS chip. What can I do to test gradually my setup? What did I did wrong? Help me out please ;-) -- Michel Belleau <michel.belleau(a)malaiwah.com>

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download cvs tarball
by Veikko Werner 27 Aug '03

27 Aug '03

hey guys, I can't download the cvs tarball onthe website (file not found) and I can't download directly from CVS (company firewall) How can I get the latest sources? Regards, Veikko

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Re: Supporting extension ROMs and beyond...
by YhLu 26 Aug '03

26 Aug '03

Ron, I try to move the vgabios to freebios2 for 2880. I put the BIOS option rom to 0xfff8c000, ( the second 48k). The result is When execute the option rom produce following output, and it seems In the option rom doesn't process bus/dev/func properly. Regards YH. INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1002, did=4752 0x55 0xaa 0x48 0xeb 0x7b 0x2e 0x65 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 biosint: # 0x1a, eax 0xb109 ebx 0x0 ecx 0x3f8 edx 0xc2cc biosint: ebp 0x16788 esp 0xfd6 edi 0x2e esi 0xe578 biosint: ip 0x29c cs 0x0 flags 0x46 0xb109: BAD DEVICE bus 0 devfn 0x0 0xb109: bus 0 devfn 0x0 reg 0x2e val 0xffff biosint: # 0x1a, eax 0xb109 ebx 0x0 ecx 0xffff edx 0xc2cc biosint: ebp 0x16788 esp 0xfd6 edi 0x14 esi 0xe578 biosint: ip 0x308 cs 0x0 flags 0x46 0xb109: BAD DEVICE bus 0 devfn 0x0 0xb109: bus 0 devfn 0x0 reg 0x14 val 0xffff biosint: # 0x1a, eax 0xb10a ebx 0x0 ecx 0x3 edx 0xc2cc biosint: ebp 0x16788 esp 0xfd6 edi 0x18 esi 0xe578 biosint: ip 0x32d cs 0x0 flags 0x86 0xb10a: BAD DEVICE bus 0 devfn 0x0 0xb10a: bus 0 devfn 0x0 reg 0x18 val 0xffffffff biosint: # 0x1a, eax 0xb108 ebx 0x0 ecx 0x84 edx 0xb108 biosint: ebp 0x10fa4 esp 0xf96 edi 0x4 esi 0x1b1 biosint: ip 0x84e9 cs 0x0 flags 0x46 0xb108: BAD DEVICE bus 0 devfn 0x0 0xb108: bus 0 devfn 0x0 reg 0x4 val 0xff biosint: # 0x1a, eax 0xb10b ebx 0x0 ecx 0xff edx 0xb10b biosint: ebp 0x10fa4 esp 0xf9a edi 0x4 esi 0x1b2 biosint: ip 0x841b cs 0x0 flags 0x46 0xb10b: BAD DEVICE bus 0 devfn 0x0 0xb10b: bus 0 devfn 0x0 reg 0x4 val 0xff biosint: # 0x1a, eax 0xb10c ebx 0x0 ecx 0x0 edx 0xb10c biosint: ebp 0x10fa4 esp 0xf9a edi 0x0 esi 0x1b4 biosint: ip 0x841b cs 0x0 flags 0x46 0xb10c: BAD DEVICE bus 0 devfn 0x0 0xb10c: bus 0 devfn 0x0 reg 0x0 val 0x0 " -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年8月11日 10:07 收件人: YhLu 抄送: SONE Takeshi; linuxbios(a)clustermatic.org 主题: re: Supporting extension ROMs and beyond... On Mon, 11 Aug 2003, YhLu wrote: > If I only want to use addon AGP Display adapter ROM, I don't need to use > VGABIOS? How about PCIBIOS? does the rom need pcibios support? if so, you need both of these modules. ron

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DIP2PLCC
by Michel Belleau 26 Aug '03

26 Aug '03

Hi. Where could I find a DIP2PLCC adapter ? I'm trying to learn LinuxBIOS but I found out that the motherboard I'm trying to get running (VIA Epia 800 fanless) has a socketed PLCC chip. I checked out on the M-Systems web site and they just have DIP32 packages of DoChips (Millenium). These should be compatible 1:1 with the PLCC version, right? All I need is an adapter right? -- Michel Belleau <michel.belleau(a)malaiwah.com>

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Re: Any freebios2 CVS snapshot ?
by ron minnich 25 Aug '03

25 Aug '03

I will try to set up snapshots via the web page this week. ron

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Linuxbios: Booting linux from flash IDE drive on epia boards?
by Hubert Denkmair 25 Aug '03

25 Aug '03

Hello, (second try) I'm planning to build my own car mp3 player on a PC basis and now found out that the VIA epia boards seem to be supported by linuxbios. I'd love to boot my mp3 player via linuxbios to get the music playing asap... unfortunatly the linuxbios-docs are not very userfriendly - I understand that it's possible to boot the epia boards via etherboot, but can i also load a kernel from IDE devices, e.g. a compact flash card mounted into a IDE compact flash drive? If not - is there any other way to load a linux-kernel really FAST in a EPIA standalone (car-) system? Would you recommand a special board, such as the EPIA-V8000, or are they all working well? Thanks a lot for your help, Hubert --- hubert(a)denkmair.de

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compatible flash chips
by Nathanael Noblet 25 Aug '03

25 Aug '03

Hello, I just received my EPIA 800 and am itching to get it up and running with freebios. I have flash parts for a board I was previously working on. I'd like to know if they are compatible, they are the same form factor (as in PLCC chips). The one in the board is a SST 39sf020a, and I have Winbond w29c020cp90b. How do I know if they are compatible? I'd rather not flash this and it not work, and then not be able to do anything with it... -- Nathanael Noblet Gnat Solutions 4604 Monterey Ave NW Calgary, AB T3B 5K4 T/F 403.288.5360 C 403.809.5368 http://www.gnat.ca/

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