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V2 Epia report
by Nathanael D. Noblet 11 Oct '03

11 Oct '03

Thanks to ron I made an romimage that is the right size, without um commenting out code here and there ;). LinuxBIOS was built fine, comes up sort of. Here's the logfile. I used FILO as my payload and well it can't find the device hda1... I've tried it with FILO 0.3 and 0.2, and get the same results... Here is the output... its long but well sorry ;) On a side note, I'm unusually happy at the fact that V2 can reboot the system without my intervention... small things seem great sometimes. Anyway, any ideas what the problem is or where to look? ***** V2 With FILO-0.3 ***** 0 LinuxBIOS-1.1.4.0Fallback Wed Oct 8 11:47:14 MDT 2003 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing dimms_write: a55a5aa5 dimms_write: b55a5aa5 dimms_write: c55a5aa5 dimms_write: d55a5aa5 dimms_write: e55a5aa5 dimms_write: f55a5aa5 NOP dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 PRECHARGE DUMMY READS dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 CBR dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 MRS dimms_read: 000001d0 dimms_read: 100001d0 dimms_read: 200001d0 dimms_read: 300001d0 dimms_read: 400001d0 dimms_read: 500001d0 NORMAL dimms_write: 55aa55aa dimms_write: 65aa55aa dimms_write: 75aa55aa dimms_write: 85aa55aa dimms_write: 95aa55aa dimms_write: a5aa55aa dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 set ref. rate enable multi-page open 00:06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00 10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50:ac 08 80 00 00 00 ff ff 40 00 ff ff ff ff ff ff 60:3f 00 00 30 e4 e4 e4 00 42 ac 65 0d 08 7f 00 00 70:00 00 00 00 00 00 00 00 01 f0 00 00 00 00 00 00 80:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00 b0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00 MA write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee vt8601 done 00:06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00 10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50:ac 08 80 00 00 00 28 28 ee 00 28 28 28 28 28 28 60:3f 00 00 30 e4 e4 e4 00 42 ac 65 0d 08 7f 00 00 70:00 00 00 00 00 00 00 00 01 f0 00 00 00 00 00 00 80:00 c1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00 b0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00 LinuxBIOS-1.1.4.0Fallback Wed Oct 8 11:47:14 MDT 2003 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.4.0Fallback Wed Oct 8 11:47:14 MDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: VIA vt8601 Northbridge Enumerating: VIA vt8231 Enumerating buses...mainboard_scan_bus: root 0000c4a0 maxbus 0 PCI: pci_scan_bus for bus 0 Read config 32 bus 0,devfn 0x0,reg 0x0,val 0x6011106 malloc Enter, size 252, free_mem_ptr 00014308 malloc 0x00014308 Read config 8 bus 0,devfn 0x0,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x8,val 0x6000005 PCI: 00:00.0 [1106/0601] enabled Read config 32 bus 0,devfn 0x8,reg 0x0,val 0x86011106 malloc Enter, size 252, free_mem_ptr 00014404 malloc 0x00014404 Read config 8 bus 0,devfn 0x8,reg 0xe,val 0x1 Read config 32 bus 0,devfn 0x8,reg 0x8,val 0x6040000 PCI: 00:01.0 [1106/8601] enabled Read config 32 bus 0,devfn 0x10,reg 0x0,val 0xffffffff PCI: devfn 0x10, bad id 0xffffffff Read config 32 bus 0,devfn 0x18,reg 0x0,val 0xffffffff PCI: devfn 0x18, bad id 0xffffffff Read config 32 bus 0,devfn 0x20,reg 0x0,val 0xffffffff PCI: devfn 0x20, bad id 0xffffffff Read config 32 bus 0,devfn 0x28,reg 0x0,val 0xffffffff PCI: devfn 0x28, bad id 0xffffffff Read config 32 bus 0,devfn 0x30,reg 0x0,val 0xffffffff PCI: devfn 0x30, bad id 0xffffffff Read config 32 bus 0,devfn 0x38,reg 0x0,val 0xffffffff PCI: devfn 0x38, bad id 0xffffffff Read config 32 bus 0,devfn 0x40,reg 0x0,val 0xffffffff PCI: devfn 0x40, bad id 0xffffffff Read config 32 bus 0,devfn 0x48,reg 0x0,val 0xffffffff PCI: devfn 0x48, bad id 0xffffffff Read config 32 bus 0,devfn 0x50,reg 0x0,val 0xffffffff PCI: devfn 0x50, bad id 0xffffffff Read config 32 bus 0,devfn 0x58,reg 0x0,val 0xffffffff PCI: devfn 0x58, bad id 0xffffffff Read config 32 bus 0,devfn 0x60,reg 0x0,val 0xffffffff PCI: devfn 0x60, bad id 0xffffffff Read config 32 bus 0,devfn 0x68,reg 0x0,val 0xffffffff PCI: devfn 0x68, bad id 0xffffffff Read config 32 bus 0,devfn 0x70,reg 0x0,val 0xffffffff PCI: devfn 0x70, bad id 0xffffffff Read config 32 bus 0,devfn 0x78,reg 0x0,val 0xffffffff PCI: devfn 0x78, bad id 0xffffffff Read config 32 bus 0,devfn 0x80,reg 0x0,val 0xffffffff PCI: devfn 0x80, bad id 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x0,val 0x82311106 malloc Enter, size 252, free_mem_ptr 00014500 malloc 0x00014500 Read config 8 bus 0,devfn 0x88,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0x88,reg 0x8,val 0x6010010 PCI: 00:11.0 [1106/8231] enabled Read config 32 bus 0,devfn 0x89,reg 0x0,val 0x5711106 malloc Enter, size 252, free_mem_ptr 000145fc malloc 0x000145fc Read config 8 bus 0,devfn 0x89,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x8,val 0x1018f06 PCI: 00:11.1 [1106/0571] enabled Read config 32 bus 0,devfn 0x8a,reg 0x0,val 0x30381106 malloc Enter, size 252, free_mem_ptr 000146f8 malloc 0x000146f8 Read config 8 bus 0,devfn 0x8a,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x8,val 0xc03001e PCI: 00:11.2 [1106/3038] enabled Read config 32 bus 0,devfn 0x8b,reg 0x0,val 0x30381106 malloc Enter, size 252, free_mem_ptr 000147f4 malloc 0x000147f4 Read config 8 bus 0,devfn 0x8b,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x8,val 0xc03001e PCI: 00:11.3 [1106/3038] enabled Read config 32 bus 0,devfn 0x8c,reg 0x0,val 0x82351106 malloc Enter, size 252, free_mem_ptr 000148f0 malloc 0x000148f0 Read config 8 bus 0,devfn 0x8c,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x8,val 0x10 PCI: 00:11.4 [1106/8235] enabled Read config 32 bus 0,devfn 0x8d,reg 0x0,val 0x30581106 malloc Enter, size 252, free_mem_ptr 000149ec malloc 0x000149ec Read config 8 bus 0,devfn 0x8d,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x8,val 0x4010040 PCI: 00:11.5 [1106/3058] enabled Read config 32 bus 0,devfn 0x8e,reg 0x0,val 0x30681106 malloc Enter, size 252, free_mem_ptr 00014ae8 malloc 0x00014ae8 Read config 8 bus 0,devfn 0x8e,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x8,val 0x7800020 PCI: 00:11.6 [1106/3068] enabled Read config 32 bus 0,devfn 0x8f,reg 0x0,val 0xffffffff PCI: devfn 0x8f, bad id 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x0,val 0x30651106 malloc Enter, size 252, free_mem_ptr 00014be4 malloc 0x00014be4 Read config 8 bus 0,devfn 0x90,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x8,val 0x2000051 PCI: 00:12.0 [1106/3065] enabled Read config 32 bus 0,devfn 0x98,reg 0x0,val 0xffffffff PCI: devfn 0x98, bad id 0xffffffff Read config 32 bus 0,devfn 0xa0,reg 0x0,val 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff Read config 32 bus 0,devfn 0xa8,reg 0x0,val 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff Read config 32 bus 0,devfn 0xb0,reg 0x0,val 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff Read config 32 bus 0,devfn 0xb8,reg 0x0,val 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff Read config 32 bus 0,devfn 0xc0,reg 0x0,val 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff Read config 32 bus 0,devfn 0xc8,reg 0x0,val 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff Read config 32 bus 0,devfn 0xd0,reg 0x0,val 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff Read config 32 bus 0,devfn 0xd8,reg 0x0,val 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff Read config 32 bus 0,devfn 0xe0,reg 0x0,val 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff Read config 32 bus 0,devfn 0xe8,reg 0x0,val 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff Read config 32 bus 0,devfn 0xf0,reg 0x0,val 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff Read config 32 bus 0,devfn 0xf8,reg 0x0,val 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff pci_scan_bridge: dev 00014404, max 0 Read config 16 bus 0,devfn 0x8,reg 0x4,val 0x7 Write config 16 bus 0, devfn 0x8, reg 0x4, val 0x0 Write config 16 bus 0, devfn 0x8, reg 0x6, val 0xffff Read config 32 bus 0,devfn 0x8,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x18, val 0xff0100 PCI: pci_scan_bus for bus 1 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0xffffffff PCI: devfn 0x0, bad id 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x0,val 0xffffffff PCI: devfn 0x8, bad id 0xffffffff Read config 32 bus 1,devfn 0x10,reg 0x0,val 0xffffffff PCI: devfn 0x10, bad id 0xffffffff Read config 32 bus 1,devfn 0x18,reg 0x0,val 0xffffffff PCI: devfn 0x18, bad id 0xffffffff Read config 32 bus 1,devfn 0x20,reg 0x0,val 0xffffffff PCI: devfn 0x20, bad id 0xffffffff Read config 32 bus 1,devfn 0x28,reg 0x0,val 0xffffffff PCI: devfn 0x28, bad id 0xffffffff Read config 32 bus 1,devfn 0x30,reg 0x0,val 0xffffffff PCI: devfn 0x30, bad id 0xffffffff Read config 32 bus 1,devfn 0x38,reg 0x0,val 0xffffffff PCI: devfn 0x38, bad id 0xffffffff Read config 32 bus 1,devfn 0x40,reg 0x0,val 0xffffffff PCI: devfn 0x40, bad id 0xffffffff Read config 32 bus 1,devfn 0x48,reg 0x0,val 0xffffffff PCI: devfn 0x48, bad id 0xffffffff Read config 32 bus 1,devfn 0x50,reg 0x0,val 0xffffffff PCI: devfn 0x50, bad id 0xffffffff Read config 32 bus 1,devfn 0x58,reg 0x0,val 0xffffffff PCI: devfn 0x58, bad id 0xffffffff Read config 32 bus 1,devfn 0x60,reg 0x0,val 0xffffffff PCI: devfn 0x60, bad id 0xffffffff Read config 32 bus 1,devfn 0x68,reg 0x0,val 0xffffffff PCI: devfn 0x68, bad id 0xffffffff Read config 32 bus 1,devfn 0x70,reg 0x0,val 0xffffffff PCI: devfn 0x70, bad id 0xffffffff Read config 32 bus 1,devfn 0x78,reg 0x0,val 0xffffffff PCI: devfn 0x78, bad id 0xffffffff Read config 32 bus 1,devfn 0x80,reg 0x0,val 0xffffffff PCI: devfn 0x80, bad id 0xffffffff Read config 32 bus 1,devfn 0x88,reg 0x0,val 0xffffffff PCI: devfn 0x88, bad id 0xffffffff Read config 32 bus 1,devfn 0x90,reg 0x0,val 0xffffffff PCI: devfn 0x90, bad id 0xffffffff Read config 32 bus 1,devfn 0x98,reg 0x0,val 0xffffffff PCI: devfn 0x98, bad id 0xffffffff Read config 32 bus 1,devfn 0xa0,reg 0x0,val 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff Read config 32 bus 1,devfn 0xa8,reg 0x0,val 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff Read config 32 bus 1,devfn 0xb0,reg 0x0,val 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff Read config 32 bus 1,devfn 0xb8,reg 0x0,val 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff Read config 32 bus 1,devfn 0xc0,reg 0x0,val 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff Read config 32 bus 1,devfn 0xc8,reg 0x0,val 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff Read config 32 bus 1,devfn 0xd0,reg 0x0,val 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff Read config 32 bus 1,devfn 0xd8,reg 0x0,val 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff Read config 32 bus 1,devfn 0xe0,reg 0x0,val 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff Read config 32 bus 1,devfn 0xe8,reg 0x0,val 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff Read config 32 bus 1,devfn 0xf0,reg 0x0,val 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff Read config 32 bus 1,devfn 0xf8,reg 0x0,val 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=01 Write config 32 bus 0, devfn 0x8, reg 0x18, val 0x10100 Write config 16 bus 0, devfn 0x8, reg 0x4, val 0x7 pci_scan_bridge returns max 1 PCI: pci_scan_bus returning with max=01 DONE mainboard_scan_bus: return 0 done dev_configure: Allocating resources... root_dev_read_resources . Root is 0000c4a0 root_dev_read_resources . link 0000c560, resource 0000c4cc compute_allocate_resource: bus 0000c560, bridge 0000c4cc, type_mask 0x100, type 0x100 vendor 0x0 device 0x0 class 0x0 Unknown device path type: 0 compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x8 PCI: 00:00.0 register 10(00000008), read-only ignoring it Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x30,val 0x0 pci_bridge_read_bases: path PCI: 00:01.0 compute_allocate_resource: bus 000144c4, bridge 00014430, type_mask 0x100, type 0x100 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 <null> compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done compute_allocate_resource: bus 000144c4, bridge 00014448, type_mask 0x1200, type 0x1200 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 <null> compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done compute_allocate_resource: bus 000144c4, bridge 00014460, type_mask 0x1200, type 0x200 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 <null> compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done DONE pci_bridge_read_bases: path PCI: 00:01.0 Read config 32 bus 0,devfn 0x8,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8,reg 0x38,val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x10,val 0x1f1 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x10,val 0xfffffff9 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x1f1 Read config 32 bus 0,devfn 0x89,reg 0x14,val 0x3f5 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x14,val 0xfffffffd Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x14,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x3f5 Read config 32 bus 0,devfn 0x89,reg 0x18,val 0x171 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x18,val 0xfffffff9 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x18,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x171 Read config 32 bus 0,devfn 0x89,reg 0x1c,val 0x375 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x1c,val 0xfffffffd Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x1c,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x375 Read config 32 bus 0,devfn 0x89,reg 0x20,val 0xcc01 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x20,val 0xfffffff1 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x20,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0xcc01 Read config 32 bus 0,devfn 0x89,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x20,val 0xfce1 Write config 32 bus 0, devfn 0x8a, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x20,val 0xffffffe1 Write config 32 bus 0, devfn 0x8a, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x20,val 0x1 Write config 32 bus 0, devfn 0x8a, reg 0x20, val 0xfce1 Read config 32 bus 0,devfn 0x8a,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x20,val 0xfce1 Write config 32 bus 0, devfn 0x8b, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x20,val 0xffffffe1 Write config 32 bus 0, devfn 0x8b, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x20,val 0x1 Write config 32 bus 0, devfn 0x8b, reg 0x20, val 0xfce1 Read config 32 bus 0,devfn 0x8b,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x10,val 0xffffff01 Write config 32 bus 0, devfn 0x8d, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x10, val 0x1 Read config 32 bus 0,devfn 0x8d,reg 0x14,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x14,val 0xfffffffd Write config 32 bus 0, devfn 0x8d, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x14,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x14, val 0x1 Read config 32 bus 0,devfn 0x8d,reg 0x18,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x18,val 0xfffffffd Write config 32 bus 0, devfn 0x8d, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x18,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x18, val 0x1 Read config 32 bus 0,devfn 0x8d,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x8e, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x10,val 0xffffff01 Write config 32 bus 0, devfn 0x8e, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x8e, reg 0x10, val 0x1 Read config 32 bus 0,devfn 0x8e,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x90, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x10,val 0xffffff01 Write config 32 bus 0, devfn 0x90, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x90, reg 0x10, val 0x1 Read config 32 bus 0,devfn 0x90,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x14,val 0xffffff00 Write config 32 bus 0, devfn 0x90, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x30,val 0x0 PCI: 00:01.0 1c * [0x00001000 - 0x00000fff] io PCI: 00:11.5 10 * [0x00001000 - 0x000010ff] io PCI: 00:11.6 10 * [0x00001400 - 0x000014ff] io PCI: 00:12.0 10 * [0x00001800 - 0x000018ff] io PCI: 00:11.2 20 * [0x00001c00 - 0x00001c1f] io PCI: 00:11.3 20 * [0x00001c20 - 0x00001c3f] io PCI: 00:11.1 20 * [0x00001c40 - 0x00001c4f] io PCI: 00:11.1 10 * [0x00001c50 - 0x00001c57] io PCI: 00:11.1 18 * [0x00001c60 - 0x00001c67] io PCI: 00:11.1 14 * [0x00001c70 - 0x00001c73] io PCI: 00:11.1 1c * [0x00001c80 - 0x00001c83] io PCI: 00:11.5 14 * [0x00001c90 - 0x00001c93] io PCI: 00:11.5 18 * [0x00001ca0 - 0x00001ca3] io <null> compute_allocate_io: base: 00001ca4 size: 000018a4 align: 12 gran: 0 done root_dev_read_resources . link 0000c560, resource 0000c4e4 compute_allocate_resource: bus 0000c560, bridge 0000c4e4, type_mask 0x200, type 0x200 vendor 0x0 device 0x0 class 0x0 Unknown device path type: 0 compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x8 PCI: 00:00.0 register 10(00000008), read-only ignoring it Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x30,val 0x0 PCI: 00:01.0 24 * [0x00000000 - 0xffffffff] prefmem PCI: 00:01.0 20 * [0x00000000 - 0xffffffff] mem PCI: 00:12.0 14 * [0x00000000 - 0x000000ff] mem <null> compute_allocate_mem: base: 00000100 size: 00000100 align: 20 gran: 0 done root_dev_read_resources DONE dev_configure: done reading resources... compute_allocate_resource: bus 0000c560, bridge 0000c4cc, type_mask 0x100, type 0x100 vendor 0x0 device 0x0 class 0x0 Unknown device path type: 0 compute_allocate_io: base: 00001000 size: 000018a4 align: 12 gran: 0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x8 PCI: 00:00.0 register 10(00000008), read-only ignoring it Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x30,val 0x0 PCI: 00:01.0 1c * [0x00001000 - 0x00000fff] io PCI: 00:11.5 10 * [0x00001000 - 0x000010ff] io PCI: 00:11.6 10 * [0x00001400 - 0x000014ff] io PCI: 00:12.0 10 * [0x00001800 - 0x000018ff] io PCI: 00:11.2 20 * [0x00001c00 - 0x00001c1f] io PCI: 00:11.3 20 * [0x00001c20 - 0x00001c3f] io PCI: 00:11.1 20 * [0x00001c40 - 0x00001c4f] io PCI: 00:11.1 10 * [0x00001c50 - 0x00001c57] io PCI: 00:11.1 18 * [0x00001c60 - 0x00001c67] io PCI: 00:11.1 14 * [0x00001c70 - 0x00001c73] io PCI: 00:11.1 1c * [0x00001c80 - 0x00001c83] io PCI: 00:11.5 14 * [0x00001c90 - 0x00001c93] io PCI: 00:11.5 18 * [0x00001ca0 - 0x00001ca3] io <null> compute_allocate_io: base: 00001ca4 size: 00000ca4 align: 12 gran: 0 done compute_allocate_resource: bus 0000c560, bridge 0000c4e4, type_mask 0x200, type 0x200 vendor 0x0 device 0x0 class 0x0 Unknown device path type: 0 compute_allocate_mem: base: feb00000 size: 00000100 align: 20 gran: 0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x8 PCI: 00:00.0 register 10(00000008), read-only ignoring it Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x30,val 0x0 PCI: 00:01.0 24 * [0xfeb00000 - 0xfeafffff] prefmem PCI: 00:01.0 20 * [0xfeb00000 - 0xfeafffff] mem PCI: 00:12.0 14 * [0xfeb00000 - 0xfeb000ff] mem <null> compute_allocate_mem: base: feb00100 size: 00000100 align: 20 gran: 0 done ASSIGN RESOURCES, bus 0 Write config 8 bus 0, devfn 0x0, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x0,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x0, reg 0xc, val 0x10 compute_allocate_resource: bus 000144c4, bridge 00014430, type_mask 0x100, type 0x100 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_io: base: 00001000 size: 00000000 align: 12 gran: 12 <null> compute_allocate_io: base: 00001000 size: 00000000 align: 12 gran: 12 done Write config 8 bus 0, devfn 0x8, reg 0x1c, val 0x10 Write config 8 bus 0, devfn 0x8, reg 0x1d, val 0xf Write config 16 bus 0, devfn 0x8, reg 0x30, val 0x0 Write config 16 bus 0, devfn 0x8, reg 0x32, val 0x0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io compute_allocate_resource: bus 000144c4, bridge 00014448, type_mask 0x1200, type 0x1200 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_prefmem: base: feb00000 size: 00000000 align: 20 gran: 20 <null> compute_allocate_prefmem: base: feb00000 size: 00000000 align: 20 gran: 20 done Write config 16 bus 0, devfn 0x8, reg 0x24, val 0xfeb0 Write config 16 bus 0, devfn 0x8, reg 0x26, val 0xfeaf Write config 32 bus 0, devfn 0x8, reg 0x28, val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x2c, val 0x0 PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmem compute_allocate_resource: bus 000144c4, bridge 00014460, type_mask 0x1200, type 0x200 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_mem: base: feb00000 size: 00000000 align: 20 gran: 20 <null> compute_allocate_mem: base: feb00000 size: 00000000 align: 20 gran: 20 done Write config 16 bus 0, devfn 0x8, reg 0x20, val 0xfeb0 Write config 16 bus 0, devfn 0x8, reg 0x22, val 0xfeaf PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem Write config 8 bus 0, devfn 0x8, reg 0xd, val 0x40 Write config 8 bus 0, devfn 0x8, reg 0x1b, val 0x40 Read config 8 bus 0,devfn 0x8,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x8, reg 0xc, val 0x10 Write config 8 bus 0, devfn 0x88, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x88,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x1c51 PCI: 00:11.1 10 <- [0x00001c50 - 0x00001c57] io Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x1c71 PCI: 00:11.1 14 <- [0x00001c70 - 0x00001c73] io Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x1c61 PCI: 00:11.1 18 <- [0x00001c60 - 0x00001c67] io Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x1c81 PCI: 00:11.1 1c <- [0x00001c80 - 0x00001c83] io Write config 32 bus 0, devfn 0x89, reg 0x20, val 0x1c41 PCI: 00:11.1 20 <- [0x00001c40 - 0x00001c4f] io Write config 8 bus 0, devfn 0x89, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x89,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x89, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x8a, reg 0x20, val 0x1c01 PCI: 00:11.2 20 <- [0x00001c00 - 0x00001c1f] io Write config 8 bus 0, devfn 0x8a, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8a,reg 0x3d,val 0x4 Write config 8 bus 0, devfn 0x8a, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x8a, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x8b, reg 0x20, val 0x1c21 PCI: 00:11.3 20 <- [0x00001c20 - 0x00001c3f] io Write config 8 bus 0, devfn 0x8b, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8b,reg 0x3d,val 0x4 Write config 8 bus 0, devfn 0x8b, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x8b, reg 0xc, val 0x10 Write config 8 bus 0, devfn 0x8c, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8c,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x8c, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x8d, reg 0x10, val 0x1001 PCI: 00:11.5 10 <- [0x00001000 - 0x000010ff] io Write config 32 bus 0, devfn 0x8d, reg 0x14, val 0x1c91 PCI: 00:11.5 14 <- [0x00001c90 - 0x00001c93] io Write config 32 bus 0, devfn 0x8d, reg 0x18, val 0x1ca1 PCI: 00:11.5 18 <- [0x00001ca0 - 0x00001ca3] io Write config 8 bus 0, devfn 0x8d, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8d,reg 0x3d,val 0x3 Write config 8 bus 0, devfn 0x8d, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x8d, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x8e, reg 0x10, val 0x1401 PCI: 00:11.6 10 <- [0x00001400 - 0x000014ff] io Write config 8 bus 0, devfn 0x8e, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8e,reg 0x3d,val 0x3 Write config 8 bus 0, devfn 0x8e, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x8e, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x90, reg 0x10, val 0x1801 PCI: 00:12.0 10 <- [0x00001800 - 0x000018ff] io Write config 32 bus 0, devfn 0x90, reg 0x14, val 0xfeb00000 PCI: 00:12.0 14 <- [0xfeb00000 - 0xfeb000ff] mem Write config 8 bus 0, devfn 0x90, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x90,reg 0x3d,val 0x1 Write config 8 bus 0, devfn 0x90, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x90, reg 0xc, val 0x10 ASSIGNED RESOURCES, bus 0 dev_configure: done setting resources... dev_configure: done vga resources... done. Enabling resourcess... Read config 16 bus 0,devfn 0x0,reg 0x4,val 0x6 PCI: 00:00.0 cmd <- 06 Write config 16 bus 0, devfn 0x0, reg 0x4, val 0x6 Read config 16 bus 0,devfn 0x8,reg 0x3e,val 0x0 PCI: 00:01.0 bridge ctrl <- 0000 Write config 16 bus 0, devfn 0x8, reg 0x3e, val 0x0 Read config 16 bus 0,devfn 0x8,reg 0x4,val 0x7 PCI: 00:01.0 cmd <- 07 Write config 16 bus 0, devfn 0x8, reg 0x4, val 0x7 Read config 16 bus 0,devfn 0x88,reg 0x4,val 0x87 PCI: 00:11.0 cmd <- 87 Write config 16 bus 0, devfn 0x88, reg 0x4, val 0x87 Read config 16 bus 0,devfn 0x89,reg 0x4,val 0x80 PCI: 00:11.1 cmd <- 81 Write config 16 bus 0, devfn 0x89, reg 0x4, val 0x81 Read config 16 bus 0,devfn 0x8a,reg 0x4,val 0x0 PCI: 00:11.2 cmd <- 01 Write config 16 bus 0, devfn 0x8a, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0x8b,reg 0x4,val 0x0 PCI: 00:11.3 cmd <- 01 Write config 16 bus 0, devfn 0x8b, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0x8c,reg 0x4,val 0x0 PCI: 00:11.4 cmd <- 00 Write config 16 bus 0, devfn 0x8c, reg 0x4, val 0x0 Read config 16 bus 0,devfn 0x8d,reg 0x4,val 0x0 PCI: 00:11.5 cmd <- 01 Write config 16 bus 0, devfn 0x8d, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0x8e,reg 0x4,val 0x0 PCI: 00:11.6 cmd <- 01 Write config 16 bus 0, devfn 0x8e, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0x90,reg 0x4,val 0x80 PCI: 00:12.0 cmd <- 83 Write config 16 bus 0, devfn 0x90, reg 0x4, val 0x83 done. Initializing devices... Devices initialized vt8231 init Read config 8 bus 0,devfn 0x88,reg 0x6c,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x6c, val 0x80 Write config 8 bus 0, devfn 0x88, reg 0x41, val 0x7f Read config 8 bus 0,devfn 0x88,reg 0x40,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x40, val 0x0 Read config 8 bus 0,devfn 0x88,reg 0x42,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x42, val 0xf0 Read config 8 bus 0,devfn 0x88,reg 0x4a,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x4a, val 0x8 Read config 8 bus 0,devfn 0x88,reg 0x4f,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x4f, val 0x8 Write config 8 bus 0, devfn 0x88, reg 0x58, val 0x3 Read config 8 bus 0,devfn 0x88,reg 0x51,val 0xff Write config 8 bus 0, devfn 0x88, reg 0x51, val 0xff Read config 8 bus 0,devfn 0x88,reg 0x6e,val 0x0 Read config 8 bus 0,devfn 0x88,reg 0x50,val 0x7 IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 Write config 8 bus 0, devfn 0x88, reg 0x50, val 0x7 Read config 8 bus 0,devfn 0x88,reg 0x4c,val 0x4 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 Write config 8 bus 0, devfn 0x88, reg 0x4c, val 0x4 Write config 8 bus 0, devfn 0x88, reg 0x46, val 0x4 Write config 8 bus 0, devfn 0x88, reg 0x47, val 0x3 Write config 8 bus 0, devfn 0x88, reg 0x6e, val 0x98 Write config 32 bus 0, devfn 0x8c, reg 0x48, val 0x4001 Write config 8 bus 0, devfn 0x8c, reg 0x41, val 0x84 Write config 32 bus 0, devfn 0x8c, reg 0x70, val 0x6001 Write config 8 bus 0, devfn 0x8c, reg 0x74, val 0x1 Write config 32 bus 0, devfn 0x8c, reg 0x90, val 0x5001 Write config 8 bus 0, devfn 0x8c, reg 0xd2, val 0x1 vt8231_init: enabling native IDE addresses Read config 8 bus 0,devfn 0x89,reg 0x42,val 0xc9 enables in reg 0x42 0xc9 Write config 8 bus 0, devfn 0x89, reg 0x42, val 0x9 Read config 8 bus 0,devfn 0x89,reg 0x42,val 0x9 enables in reg 0x42 read back as 0x9 Read config 8 bus 0,devfn 0x89,reg 0x40,val 0x8 enables in reg 0x40 0x8 Write config 8 bus 0, devfn 0x89, reg 0x40, val 0xb Read config 8 bus 0,devfn 0x89,reg 0x40,val 0xb enables in reg 0x40 read back as 0xb Read config 8 bus 0,devfn 0x89,reg 0x41,val 0x2 Write config 8 bus 0, devfn 0x89, reg 0x41, val 0xf2 Read config 8 bus 0,devfn 0x89,reg 0x43,val 0x3a Write config 8 bus 0, devfn 0x89, reg 0x43, val 0x35 Write config 8 bus 0, devfn 0x89, reg 0x44, val 0x18 Write config 8 bus 0, devfn 0x89, reg 0x45, val 0x1c Read config 8 bus 0,devfn 0x89,reg 0x9,val 0x8f enables in reg 0x9 0x8f Write config 8 bus 0, devfn 0x89, reg 0x9, val 0x8f Read config 8 bus 0,devfn 0x89,reg 0x9,val 0x8f enables in reg 0x9 read back as 0x8f Read config 8 bus 0,devfn 0x89,reg 0x4,val 0x81 command in reg 0x4 0x81 Write config 8 bus 0, devfn 0x89, reg 0x4, val 0x7 Read config 8 bus 0,devfn 0x89,reg 0x4,val 0x7 command in reg 0x4 reads back as 0x7 Write config 8 bus 0, devfn 0x88, reg 0x40, val 0x54 Ethernet fixup Configuring VIA LAN Read config 8 bus 0,devfn 0x90,reg 0x4,val 0x83 Write config 8 bus 0, devfn 0x90, reg 0x4, val 0x3 RTC Init Invalid CMOS LB checksum FUCK! ROUTING FIXUP! pci_routing_fixup: dev is 00014500 Write config 8 bus 0, devfn 0x88, reg 0x55, val 0xb0 Write config 8 bus 0, devfn 0x88, reg 0x56, val 0xa5 Write config 8 bus 0, devfn 0x88, reg 0x57, val 0xc0 setting southbridge Read config 8 bus 0,devfn 0x88,reg 0x3d,val 0x0 Read config 8 bus 0,devfn 0x89,reg 0x3d,val 0x1 Assigning IRQ 11 to 0:11.1 Write config 8 bus 0, devfn 0x89, reg 0x3c, val 0xb Read config 8 bus 0,devfn 0x89,reg 0x3c,val 0xe Readback = 14 pci_level_irq: current ints are 0x0 pci_level_irq: try to set ints 0x800 Read config 8 bus 0,devfn 0x8a,reg 0x3d,val 0x4 Assigning IRQ 12 to 0:11.2 Write config 8 bus 0, devfn 0x8a, reg 0x3c, val 0xc Read config 8 bus 0,devfn 0x8a,reg 0x3c,val 0xc Readback = 12 pci_level_irq: current ints are 0x800 pci_level_irq: try to set ints 0x1800 pci_level_irq: lower order bits are wrong: want 0x8, got 0x18 Read config 8 bus 0,devfn 0x8b,reg 0x3d,val 0x4 Assigning IRQ 12 to 0:11.3 Write config 8 bus 0, devfn 0x8b, reg 0x3c, val 0xc Read config 8 bus 0,devfn 0x8b,reg 0x3c,val 0xc Readback = 12 pci_level_irq: current ints are 0x1800 pci_level_irq: try to set ints 0x1800 pci_level_irq: lower order bits are wrong: want 0x8, got 0x18 Read config 8 bus 0,devfn 0x8c,reg 0x3d,val 0x0 Read config 8 bus 0,devfn 0x8d,reg 0x3d,val 0x3 Assigning IRQ 10 to 0:11.5 Write config 8 bus 0, devfn 0x8d, reg 0x3c, val 0xa Read config 8 bus 0,devfn 0x8d,reg 0x3c,val 0xa Readback = 10 pci_level_irq: current ints are 0x1800 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8e,reg 0x3d,val 0x3 Assigning IRQ 10 to 0:11.6 Write config 8 bus 0, devfn 0x8e, reg 0x3c, val 0xa Read config 8 bus 0,devfn 0x8e,reg 0x3c,val 0xa Readback = 10 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting ethernet Read config 8 bus 0,devfn 0x90,reg 0x3d,val 0x1 Assigning IRQ 11 to 0:12.0 Write config 8 bus 0, devfn 0x90, reg 0x3c, val 0xb Read config 8 bus 0,devfn 0x90,reg 0x3c,val 0xb Readback = 11 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting pci slot pci_routing_fixup: DONE Read config 8 bus 0,devfn 0x0,reg 0x5a,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5b,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5c,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5d,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5e,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5f,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x56,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x57,val 0x28 I would set ram size to 0x50000 Kbytes mem[0].basek = 00000000 mem[0].sizek = 00050000 mem[1].basek = 00000000 mem[1].sizek = 00000000 mem[2].basek = 00000000 mem[2].sizek = 00000000 mem[3].basek = 00000000 mem[3].sizek = 00000000 mem[4].basek = 00000000 mem[4].sizek = 00000000 mem[5].basek = 00000000 mem[5].sizek = 00000000 mem[6].basek = 00000000 mem[6].sizek = 00000000 mem[7].basek = 00000000 mem[7].sizek = 00000000 mem[8].basek = 00000000 mem[8].sizek = 00000000 mem[9].basek = 00000000 mem[9].sizek = 00000000 totalram: 320M Initializing CPU #0 Updating microcode microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 256MB, type WB Setting variable MTRR 1, base: 256MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x03 Feature flags : 0x00803035 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized BOOT CPU is 0 Checking IRQ routing tables... /usr/src/freebios2/src/arch/i386/boot/pirq_routing.c: 29:check_pirq_routing_table() - irq_routing_table located at: 0x0000a020 done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...succeed Wrote linuxbios table at: 00000500 - 00000ae0 checksum e367 VT8601 random fixup ... Write config 8 bus 0, devfn 0x0, reg 0x70, val 0xc0 Write config 8 bus 0, devfn 0x0, reg 0x71, val 0x88 Write config 8 bus 0, devfn 0x0, reg 0x72, val 0xec Write config 8 bus 0, devfn 0x0, reg 0x73, val 0xc Write config 8 bus 0, devfn 0x0, reg 0x74, val 0xe Write config 8 bus 0, devfn 0x0, reg 0x75, val 0x81 Write config 8 bus 0, devfn 0x0, reg 0x76, val 0x52 pci_routing_fixup: dev is 00014500 Write config 8 bus 0, devfn 0x88, reg 0x55, val 0xb0 Write config 8 bus 0, devfn 0x88, reg 0x56, val 0xa5 Write config 8 bus 0, devfn 0x88, reg 0x57, val 0xc0 setting southbridge Read config 8 bus 0,devfn 0x88,reg 0x3d,val 0x0 Read config 8 bus 0,devfn 0x89,reg 0x3d,val 0x1 Assigning IRQ 11 to 0:11.1 Write config 8 bus 0, devfn 0x89, reg 0x3c, val 0xb Read config 8 bus 0,devfn 0x89,reg 0x3c,val 0xe Readback = 14 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8a,reg 0x3d,val 0x4 Assigning IRQ 12 to 0:11.2 Write config 8 bus 0, devfn 0x8a, reg 0x3c, val 0xc Read config 8 bus 0,devfn 0x8a,reg 0x3c,val 0xc Readback = 12 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8b,reg 0x3d,val 0x4 Assigning IRQ 12 to 0:11.3 Write config 8 bus 0, devfn 0x8b, reg 0x3c, val 0xc Read config 8 bus 0,devfn 0x8b,reg 0x3c,val 0xc Readback = 12 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8c,reg 0x3d,val 0x0 Read config 8 bus 0,devfn 0x8d,reg 0x3d,val 0x3 Assigning IRQ 10 to 0:11.5 Write config 8 bus 0, devfn 0x8d, reg 0x3c, val 0xa Read config 8 bus 0,devfn 0x8d,reg 0x3c,val 0xa Readback = 10 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8e,reg 0x3d,val 0x3 Assigning IRQ 10 to 0:11.6 Write config 8 bus 0, devfn 0x8e, reg 0x3c, val 0xa Read config 8 bus 0,devfn 0x8e,reg 0x3c,val 0xa Readback = 10 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting ethernet Read config 8 bus 0,devfn 0x90,reg 0x3d,val 0x1 Assigning IRQ 11 to 0:12.0 Write config 8 bus 0, devfn 0x90, reg 0x3c, val 0xb Read config 8 bus 0,devfn 0x90,reg 0x3c,val 0xb Readback = 11 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting pci slot pci_routing_fixup: DONE 0x0: Read config 8 bus 0,devfn 0x88,reg 0x0,val 0x6 06 Read config 8 bus 0,devfn 0x88,reg 0x1,val 0x11 11 Read config 8 bus 0,devfn 0x88,reg 0x2,val 0x31 31 Read config 8 bus 0,devfn 0x88,reg 0x3,val 0x82 82 Read config 8 bus 0,devfn 0x88,reg 0x4,val 0x87 87 Read config 8 bus 0,devfn 0x88,reg 0x5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6,val 0x10 10 Read config 8 bus 0,devfn 0x88,reg 0x7,val 0x2 02 Read config 8 bus 0,devfn 0x88,reg 0x8,val 0x10 10 Read config 8 bus 0,devfn 0x88,reg 0x9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa,val 0x1 01 Read config 8 bus 0,devfn 0x88,reg 0xb,val 0x6 06 Read config 8 bus 0,devfn 0x88,reg 0xc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe,val 0x80 80 Read config 8 bus 0,devfn 0x88,reg 0xf,val 0x0 00 0x10: Read config 8 bus 0,devfn 0x88,reg 0x10,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x11,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x12,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x13,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x14,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x15,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x16,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x17,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x18,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x19,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1f,val 0x0 00 0x20: Read config 8 bus 0,devfn 0x88,reg 0x20,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x21,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x22,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x23,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x24,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x25,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x26,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x27,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x28,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x29,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2f,val 0x0 00 0x30: Read config 8 bus 0,devfn 0x88,reg 0x30,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x31,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x32,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x33,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x34,val 0xc0 c0 Read config 8 bus 0,devfn 0x88,reg 0x35,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x36,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x37,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x38,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x39,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3f,val 0x0 00 0x40: Read config 8 bus 0,devfn 0x88,reg 0x40,val 0x54 54 Read config 8 bus 0,devfn 0x88,reg 0x41,val 0x7f 7f Read config 8 bus 0,devfn 0x88,reg 0x42,val 0xf0 f0 Read config 8 bus 0,devfn 0x88,reg 0x43,val 0x20 20 Read config 8 bus 0,devfn 0x88,reg 0x44,val 0x4e 4e Read config 8 bus 0,devfn 0x88,reg 0x45,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x46,val 0x4 04 Read config 8 bus 0,devfn 0x88,reg 0x47,val 0x3 03 Read config 8 bus 0,devfn 0x88,reg 0x48,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x49,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x4a,val 0x8 08 Read config 8 bus 0,devfn 0x88,reg 0x4b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x4c,val 0x4 04 Read config 8 bus 0,devfn 0x88,reg 0x4d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x4e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x4f,val 0x8 08 0x50: Read config 8 bus 0,devfn 0x88,reg 0x50,val 0x7 07 Read config 8 bus 0,devfn 0x88,reg 0x51,val 0xff ff Read config 8 bus 0,devfn 0x88,reg 0x52,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x53,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x54,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x55,val 0xb0 b0 Read config 8 bus 0,devfn 0x88,reg 0x56,val 0xa5 a5 Read config 8 bus 0,devfn 0x88,reg 0x57,val 0xc0 c0 Read config 8 bus 0,devfn 0x88,reg 0x58,val 0x3 03 Read config 8 bus 0,devfn 0x88,reg 0x59,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5f,val 0x0 00 0x60: Read config 8 bus 0,devfn 0x88,reg 0x60,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x61,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x62,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x63,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x64,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x65,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x66,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x67,val 0x8 08 Read config 8 bus 0,devfn 0x88,reg 0x68,val 0x1 01 Read config 8 bus 0,devfn 0x88,reg 0x69,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6c,val 0x80 80 Read config 8 bus 0,devfn 0x88,reg 0x6d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6e,val 0x98 98 Read config 8 bus 0,devfn 0x88,reg 0x6f,val 0x0 00 0x70: Read config 8 bus 0,devfn 0x88,reg 0x70,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x71,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x72,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x73,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x74,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x75,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x76,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x77,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x78,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x79,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7c,val 0x20 20 Read config 8 bus 0,devfn 0x88,reg 0x7d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7f,val 0x0 00 0x80: Read config 8 bus 0,devfn 0x88,reg 0x80,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x81,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x82,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x83,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x84,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x85,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x86,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x87,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x88,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x89,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8f,val 0x0 00 0x90: Read config 8 bus 0,devfn 0x88,reg 0x90,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x91,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x92,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x93,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x94,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x95,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x96,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x97,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x98,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x99,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9f,val 0x0 00 0xa0: Read config 8 bus 0,devfn 0x88,reg 0xa0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xaa,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xab,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xac,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xad,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xae,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xaf,val 0x0 00 0xb0: Read config 8 bus 0,devfn 0x88,reg 0xb0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xba,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbe,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbf,val 0x0 00 0xc0: Read config 8 bus 0,devfn 0x88,reg 0xc0,val 0x1 01 Read config 8 bus 0,devfn 0x88,reg 0xc1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc2,val 0x2 02 Read config 8 bus 0,devfn 0x88,reg 0xc3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xca,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xcb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xcc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xcd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xce,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xcf,val 0x0 00 0xd0: Read config 8 bus 0,devfn 0x88,reg 0xd0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xda,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xdb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xdc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xdd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xde,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xdf,val 0x0 00 0xe0: Read config 8 bus 0,devfn 0x88,reg 0xe0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xea,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xeb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xec,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xed,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xee,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xef,val 0x0 00 0xf0: Read config 8 bus 0,devfn 0x88,reg 0xf0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf6,val 0x15 15 Read config 8 bus 0,devfn 0x88,reg 0xf7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfa,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfe,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xff,val 0x0 00 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 23:stream_init() - rom_stream: 0xfffc0000 - 0xfffeffff Found ELF candiate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 00014ce0 malloc 0x00014ce0 New segment addr 0x100000 size 0x1fd70 offset 0xa0 filesize 0x66e8 (cleaned up) New segment addr 0x100000 size 0x1fd70 offset 0xa0 filesize 0x66e8 lb: [0x0000000000004000, 0x0000000000018308) malloc Enter, size 32, free_mem_ptr 00014d00 malloc 0x00014d00 New segment addr 0x11fd80 size 0x48 offset 0x67a0 filesize 0x48 (cleaned up) New segment addr 0x11fd80 size 0x48 offset 0x67a0 filesize 0x48 lb: [0x0000000000004000, 0x0000000000018308) Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000001fd70 filesz: 0x00000000000066e8 [ 0x0000000000100000, 00000000001066e8, 0x000000000011fd70) <- 00000000000000a0 Clearing Segment: addr: 0x00000000001066e8 memsz: 0x0000000000019688 Loading Segment: addr: 0x000000000011fd80 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x000000000011fd80, 000000000011fdc8, 0x000000000011fdc8) <- 00000000000067a0 Loaded segments verified segments closed down stream Jumping to boot code at 0x104718 entry = 0x00104718 lb_start = 0x00004000 lb_size = 0x00014308 adjust = 0x13fe7cf8 buffer = 0x13fd79f0 elf_boot_notes = 0x0000dd60 adjusted_boot_notes = 0x13ff5a58 FILO version 0.3 (root@kioskdev) Tue Oct 7 18:37:11 MDT 2003 Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 Detected floating bus No such device boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 No such device -- Nathanael D. Noblet <nathanael(a)gnat.ca> Gnat Solutions

5 16

[COMMIT] freebios2 How much have I broken?
by ebiederman＠lnxi.com 11 Oct '03

11 Oct '03

This is a flush of all my pending Opteron bug fixes. Plus a new version of romcc, with all of the outstanding changes. Plus some very recent work on getting enables and disables of devices working properly. Plus my reindenting/beautify tirad on the via epia code. The guts look good but I suspect I have introduced some problems with ports other than the hdama. Especially with the configuration updates. My apologies for not looking those up and fixing them but I need to go home, and my queue of pending changes is far to long already. Eric - 1.1.5 - O2, enums, and switch statements work in romcc - Support for compiling romcc on non x86 platforms - new romc options -msse and -mmmx for specifying extra registers to use - Bug fixes to device the device disable/enable framework and an amd8111 implementation - Move the link specification to the chip specification instead of the path - Allow specifying devices with internal bridges. - Initial via epia support - Opteron errata fixes VS: ---------------------------------------------------------------------- CVS: Enter Log. Lines beginning with `CVS:' are removed automatically CVS: CVS: Committing in . CVS: CVS: Modified Files: CVS: NEWS src/arch/i386/config/make.base CVS: src/arch/i386/lib/console.inc src/arch/i386/lib/cpu.c CVS: src/boot/hardwaremain.c src/config/Config src/config/Config.lb CVS: src/config/Options.lb src/cpu/k8/cpufixup.c src/cpu/p6/mtrr.c CVS: src/devices/chip.c src/devices/device.c CVS: src/devices/device_util.c src/devices/hypertransport.c CVS: src/devices/pci_device.c src/devices/root_device.c CVS: src/include/cpu/k8/mtrr.h src/include/device/chip.h CVS: src/include/device/device.h src/include/device/path.h CVS: src/mainboard/amd/quartet/mptable.c CVS: src/mainboard/arima/hdama/Config CVS: src/mainboard/arima/hdama/Config.lb CVS: src/mainboard/arima/hdama/auto.c CVS: src/mainboard/arima/hdama/failover.c CVS: src/mainboard/arima/hdama/irq_tables.c CVS: src/mainboard/arima/hdama/mainboard.c CVS: src/mainboard/arima/hdama/mptable.c CVS: src/northbridge/amd/amdk8/Config CVS: src/northbridge/amd/amdk8/Config.lb CVS: src/northbridge/amd/amdk8/coherent_ht.c CVS: src/northbridge/amd/amdk8/misc_control.c CVS: src/northbridge/amd/amdk8/northbridge.c CVS: src/northbridge/amd/amdk8/raminit.c CVS: src/northbridge/via/vt8601/northbridge.c src/pc80/vgabios.c CVS: src/pc80/vgachip.h src/southbridge/amd/amd8111/Config.lb CVS: src/southbridge/amd/amd8111/amd8111_acpi.c CVS: src/southbridge/amd/amd8111/amd8111_early_smbus.c CVS: src/southbridge/amd/amd8111/amd8111_ide.c CVS: src/southbridge/amd/amd8111/amd8111_lpc.c CVS: src/southbridge/amd/amd8111/amd8111_usb.c CVS: src/southbridge/amd/amd8111/amd8111_usb2.c CVS: src/southbridge/amd/amd8131/amd8131_bridge.c CVS: src/southbridge/via/vt8231/chip.h CVS: src/southbridge/via/vt8231/vt8231.c CVS: src/southbridge/via/vt8231/vt8231_early_serial.c CVS: src/southbridge/via/vt8231/vt8231_early_smbus.c CVS: src/superio/NSC/pc87360/chip.h CVS: src/superio/NSC/pc87360/superio.c targets/buildtarget CVS: targets/arima/hdama/Config.lb util/newconfig/Makefile CVS: util/newconfig/config.g util/options/build_opt_tbl.c CVS: util/romcc/Makefile util/romcc/romcc.c CVS: util/romcc/tests/simple_test60.c CVS: Added Files: CVS: src/northbridge/amd/amdk8/cpu_rev.c CVS: src/northbridge/amd/amdk8/mcf0_control.c CVS: src/southbridge/amd/amd8111/amd8111.c CVS: src/southbridge/amd/amd8111/amd8111.h CVS: src/southbridge/amd/amd8111/amd8111_ac97.c CVS: src/southbridge/amd/amd8111/amd8111_nic.c CVS: util/romcc/results/linux_test1.out CVS: util/romcc/results/linux_test2.out CVS: util/romcc/results/linux_test3.out CVS: util/romcc/results/linux_test4.out CVS: util/romcc/results/linux_test5.out CVS: util/romcc/results/linux_test6.out CVS: util/romcc/results/linux_test7.out CVS: util/romcc/tests/fail_test4.c util/romcc/tests/fail_test5.c CVS: util/romcc/tests/linux_console.h CVS: util/romcc/tests/linux_syscall.h CVS: util/romcc/tests/linux_test1.c util/romcc/tests/linux_test2.c CVS: util/romcc/tests/linux_test3.c util/romcc/tests/linux_test4.c CVS: util/romcc/tests/linux_test5.c util/romcc/tests/linux_test6.c CVS: util/romcc/tests/linux_test7.c CVS: util/romcc/tests/linuxi386_syscall.h CVS: util/romcc/tests/raminit_test6.c CVS: util/romcc/tests/simple_test57.c CVS: util/romcc/tests/simple_test58.c CVS: util/romcc/tests/simple_test61.c CVS: util/romcc/tests/simple_test62.c CVS: util/romcc/tests/simple_test63.c CVS: util/romcc/tests/simple_test64.c CVS: util/romcc/tests/simple_test65.c CVS: util/romcc/tests/simple_test66.c CVS: util/romcc/tests/simple_test67.c CVS: util/romcc/tests/simple_test68.c CVS: ----------------------------------------------------------------------

1 0

HDAMA + FILO
by Craig C. Forney 10 Oct '03

10 Oct '03

I was able to get FILO up as a PAYLOAD for Linuxbios in a very short time. And it was able to load and start executing either memtest86 or the Linux kernel off of an IDE disk using GRUB. Unfortunately when Linux is booting up and attempts to mount the root file system, it chokes complaining that it can't mount the root device (the entry is fine, and linux reports the root device properly as it tries to mount it). When I stick back in the stock Phoenix BIOS, the same disk/kernel boots up just fine and has no problems whatsoever mounting the root device. I suspect that maybe FILO has done something naughty to the IDE registers, as I think the root mount is the first work the kernel is doing on the disk. The kernel can see the CDROM (as well as all the other non-IDE devices). Anybody have any ideas on this? Craig C. Forney Opus Innovations LLC

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Hdama + etherboot problems
by Craig C Forney 10 Oct '03

10 Oct '03

I am attempting to get through the logistics of getting Linuxbios working on an Arima HDAMA board. I have run into a few problems, some of which I have been able to solve, and some of which have me stumped. I'm compiling everything on a stock SuSE 8.2 Professional release with the stock compilers on an Intel-based laptop (I ran into problems earlier trying to make the Linuxbios native on the Arima board, as there are some in-line assembly code issues that still need to be resolved). I've been able to create a linuxbios.rom using the latest code from sourceforge (earlier today). I changed raminit.c to accommodate 200Mhz registered memory (this case is missing in raminit.c), as this is the memory that I have. I downloaded etherboot 3.0 (5.3.1) from www.etherboot.org and compiled ide_disk.zelf (using the -DCONFIG_X86_64 option), and then used ide_disk.zelf as the payload in creating linuxbios.rom. I programmed a FLASH part with linuxbios.rom and turned on the machine. It goes through what looks like reasonable startup stuff, finds the etherboot payload, loads it, and tries to run it. It then appears to go back and reboot before anything interesting is reported happening in etherboot, and then repeats this cycle forever. I don't like the looks of the irq_routing_table checksum error, but I'm not sure if it is a problem or not, at this point. I notice that during compilation that the table has been set to be short compared to the initializers and gets a warning. Increasing the size, and making the compile errors go away does not seem to get rid of the checksum issue during run time. The last part of the output before loading etherboot follows: ------------------------------------------------ Output to serial port Setting up local apic... apic_id: 16777216 done. CPU #1 Initialized secondary_cpu_init 1/1 All AP CPUs stopped Checking IRQ onsistent IRQ routing table size /usr/src/freebios2/src/arch/i386/boot/pirq_routing.c: 29:check_pirq_routing_table() - irq_routing_table located at: 0x0000b8e0 /usr/src/freebios2/src/arch/i386/boot/pirq_routing.c: 37:check_pirq_routing_table() - checksum is: 0x35 but should be: 0x48 /usr/src/freebios2/src/arch - checksum error in irq routing table done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...succeed Wrote the mp table end at: 00000020 - 00000224 Wrote linuxbios table at: 00000500 - 00000af0 checksum 4540 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 Found ELF candiate at offset 0 Loading Etherboot version: 5.3.1 Dropping non PT_LOAD segment New segment addr 0x20000 size 0x18817 offset 0xb0 filesize 0x3cea (cleaned up) New segment addr 0x20000 size 0x18817 offset 0xb0 filesize 0x3cea Loading Segment: addr: 0x0000000000020000 memsz: 0x0000000000018817 filesz: 0x0000000000003cea Clearing Segment: addr: 0x0000000000023cea memsz: 0x0000000000014b2d Jumping to boot code at 0x20000 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.4.0Fallback Tue Oct 7 16:22:20 PDT 2003 rebooting... ------------------------------------------------ End of output I'd appreciate any advice on what I might be doing wrong. I tried to use the ide_disk.zelf from YH that was sent out yesterday (below), but I was not able to get it to work at all (the decoded file was not in ELF format, and was not recognized by Linuxbios as a valid ELF file.) I'd like to get another copy of tg3--ide_disk.zelf, if possible. > From: YhLu <YhLu(a)tyan.com> > To: Stefan Reinauer <stepan(a)suse.de> > Cc: linuxbios(a)clustermatic.org > Subject: re: K8 MTRR reboot on Solo > Date: Mon, 6 Oct 2003 10:37:26 -0700 > > This message is in MIME format. Since your mail reader does > not understand this format, some or all of this message may > not be legible. > > ------_=_NextPart_000_01C38C30.8253BA70 > Content-Type: text/plain; > charset="GB2312" > Content-Transfer-Encoding: quoted-printable > > I enabled it, and use X86-64 bin to make elf image with > mkelfimage 2.5. > > Please try my zelf instead. > > Regards > > YH. > I'm not sure what "use X86-64 bin to make elf image with mkelfimage 2.5" means above. Is this critical, or is the zelf created by the etherboot code acceptable? Also, I would like to get memtest86 to work as a payload too, but I'm not sure what I need to do to make that work. I was able to make the modifications necessary to get it to run on the Opteron when loaded from the stock Arima Phoenix BIOS. Any assistance or advice on these problems appreciated. I'm sure I am overlooking some things here. I apologize for the long-windedness of all this. Regards, Craig Forney Opus Innovations LLC

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Re: The Great Cheap EPIA contest.
by David Hendricks 09 Oct '03

09 Oct '03

Case: http://www.axiontech.com/prdt.php?item=34633 $72 EPIA 8000A: http://www.axiontech.com/prdt.php?item=34667 $91 Factory installation: $25 Total: $188 per node, plus S&H. Plus we have to flash the BIOSes ourselves which would be a hassle since we can't just boot off a Clustermatic cdrom. On the plus side, we've ordered from these guys before and they didn't screw us on anything I ordered, and they accept government PO's. Meh, I tried.

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Re: romcc portability (cont)
by ebiederman＠lnxi.com 09 Oct '03

09 Oct '03

<standard rant> Please use the list for basic stuff like this. As the reply at least is educational to multiple people. </standard rant> "Peter Fox" <peter.fox(a)ifrsys.com> writes: > For various reasons I won't bore you with, I'm trying out the > freebios2 stuff on freebsd. I had a couple of problems compiling > romcc that you might like to address in the next version: > > Freebsd doesn't have <stdint.h>. > > I forgot to mention - I just commented out <stdint.h> and it seemed to compile > ok without it, so I guess you don't actually need to include it. I do use uint8_t, uint16_t, and uint32_t so stdint.h is needed. It sounds like Freebsd may be defining these somewhere else at the moment. Short of building a configure script I really can't address this. If someone would like to contribute a configure script I would happily accept one. I am busy with more core aspects of the code at the moment. I totally support the idea of building on Freebsd. There is nothing inherently Linux specific about LinuxBIOS at this point > __error() clashes with an entry in <errno.h> - perhaps you should > prefix your functions by '_romcc_', rather than '__' ? Ouch this is a problem. Everything with a leading underscore is reserved to the implementation. Double underscore is reserved for global scope and a single underscore is reserved for file scope definitions. So this is my bug. I have just changed those three instances from __ to romcc_ and all looks good here. I will see what I can do about committing these changes. Eric

1 0

romcc error in smbus code
by Stefan Reinauer 09 Oct '03

09 Oct '03

Hi Eric, I recently added the function smbus_write_byte() to src/southbridge/amd/amd8111/amd8111_early_smbus.c. if the code within #if 0 in that function is enabled, I get the following internal compiler error: ./romcc -mcpu=k8 -O ./auto.E > auto.inc <built-in>:1.0: warning: edge: <built-in>:1.0: warning: 0x2fe7e40 __inw amd8111_early_smbus.c:120.39: warning: edge: amd8111_early_smbus.c:120.39: warning: 0x2fe80e0 copy <built-in>:1.0: warning: edge: <built-in>:1.0: warning: 0x3126060 copy <built-in>:1.0: warning: edge: <built-in>:1.0: warning: 0x2fea8d0 __inw amd8111_early_smbus.c:125.63: warning: edge: amd8111_early_smbus.c:125.63: warning: 0x2feab70 copy <built-in>:1.0: warning: edge: <built-in>:1.0: warning: 0x2feba50 __inw io.h:39.1: warning: edge: io.h:39.1: warning: 0x2febb70 copy amd8111_early_smbus.c:128.48: warning: 0x2febcf0 copy <built-in>:1.0: warning: edge: <built-in>:1.0: warning: 0x2fe6450 __inw auto.c:102.45: warning: def: auto.c:102.45: warning: 0x2fe5020 copy amd8111_early_smbus.c:131.33: warning: 0x2fec520 copy auto.c:102.45: 0x2fe5020 copy Internal compiler error: live range with already used color %ax Is the code running out of registers? What's happening here? Stefan -- Architecture Team SuSE Linux AG

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LNXI hdama merge status...
by ebiederman＠lnxi.com 08 Oct '03

08 Oct '03

I have just gone through and done the bulk of the merge work, between my internal stable tree and the main LinuxBIOS tree. I have a bunch of details to check to make certain things are working. And to double check I have not done something stupid, but so far things look promising. Among other things I have gotten a 32 bit kernel without mptable support to boot and find it's irqs successfully. Although I will agree that not scanning all pci busses just in case something might go wrong is a reasonable conservative approach. Anyway properly handling irqs, and getting the LinuxBIOS interfaces right looks like the next step for v2.0. Later, Eric

1 0

V2 Epia
by Nathanael Noblet 08 Oct '03

08 Oct '03

Hello, So I don't have an etherboot setup, and am trying to build the epia target. I would like the payload to be filo.elf and have changed the payload options. Then I couldn't get it done because with the fallback image it was saying the romimage was too large. Well I don't use a fallback image anyway (or never have) so commented out everything that was related to FALLBACK I could find in the Config.lb file. It wouldn't compile after that because elfboot.c had missing link for boot_successful() so I commented that out.. anyway I didn't look at the boot successful function, but suffice it to say it didn't work. It built and flashed and all that but it didn't come up. So I'm wondering what is the preferred method in V2 to not have a fallback image. The other thing I noticed is that my linuxbios.rom file is only 192Kb instead of 256kb... Is that why the fallback image wouldn't work? -- Nathanael Noblet Gnat Solutions 4604 Monterey Ave NW Calgary, AB T3B 5K4 T/F 403.288.5360 C 403.809.5368 http://www.gnat.ca/

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FILO 0.3
by SONE Takeshi 08 Oct '03

08 Oct '03

I released FILO version 0.3, featuring bzImage loader. Steve Gehlbach has helped me a lot. Version 0.3 ts1 2003-10-07 * Added loader for Linux bzImage/zImage/Image (a.k.a. /vmlinuz). Many thanks to Steve Gehlbach <steve(a)nexpath.com> for early work on this. * New "context switch" routine to unify the assembly starters for ELF and Linux, and even the C startup. This reduced the amount of assembly code. * Debug prints are now automatically prefixed with function names. * Lots of internal tweaks. It can be downloaded from http://te.to/~ts1/filo/. -- Takeshi

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