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39711 discussions

code flow
by Frank 22 Mar '04

22 Mar '04

Is there a document that describes the code flow for freebios. Specifically, I'm trying to figure out the booting process. I've configured and compiled the code for the sis550 but I don't see how the LPC is being configured. The only way I can get the ipl.S to be assembled is to define the docipl rule in the config file. I need to use the LPC bridge for a custom board I will eventually be porting freebios to but I still want to be able to boot from the standard flash device. The way the existing code works is the only way you can compile in the ipl stuff is to define docipl. I will also need to access the LPC bridge to do I2C when reading the spd on the sodimm module. Can anyone suggest how i can include the ipl stuff without the docipl stuff. Another eason I don't want to use the docipl stuff is because the python scripts changes the rom base address to 0x80000. I want the rom base address to be 0xf0000. Any help will greatly appreciated... __________________________________ Do you Yahoo!? Yahoo! Mail - More reliable, more storage, less spam http://mail.yahoo.com

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Geode gx2
by Ina Miranda 21 Mar '04

21 Mar '04

Hi, I’d just like to ask if LinuxBIOS is compatible with Geode GX2 chipset. Thanks, Ina --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.567 / Virus Database: 358 - Release Date: 1/24/2004

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Status AMD64 ram init
by Stefan Reinauer 20 Mar '04

20 Mar '04

Excerpt from current solo build: LinuxBIOS-1.1.6.0-Fallback Fr Mär 19 14:43:18 CET 2004 starting... setting up resource map....done. ht reset - LinuxBIOS-1.1.6.0-Fallback Fr Mär 19 14:43:18 CET 2004 starting... setting up resource map....done. Ram1.00 Ram2.00 Bad SPD value Using the default hynix PC2100U 256MB DDR 266MHz CL2.5 modules. I'm building a debug image which dumps the spd roms... Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development

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Unions?
by Stefan Reinauer 19 Mar '04

19 Mar '04

./romcc -mcpu=k8 -O2 ./auto.E > auto.inc path.h:31.13: unions not yet supported Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development

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AMD K8 memory bug with more than 2 banks
by Craig C Forney 18 Mar '04

18 Mar '04

I ran into a problem with a Dual Opeteron cPCI board we developed with 4 banks of memory. It showed up when the third and fourth banks were populated. I narrowed it down to a problem in src/amd/amdk8/raminit.c. There is a '+' where there should be a '*', causing the SPD settings to get corrupted, which causes bizarre results which varies depending on the memory parameters read from the DIMMs. One possible result is that some DIMMs will work marginally because one or more of their settings has been corrupted. This patch seems to resolve the problem. I'm not sure if anybody else out there is accessing 4 banks of memory via the Opteron memory interface, so it might be just us, but it would probably be a good idea to commit this patch to the freebios2 source tree. Can someone take this on? Thanks, Craig Forney Opus Innovations LLC diff -Naur raminit.c.orig raminit.c --- raminit.c.orig 2004-03-16 13:25:05.000000000 -0800 +++ raminit.c 2004-03-16 13:42:30.000000000 -0800 @@ -924,7 +924,7 @@ sz.side2 = 0; } map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); - map &= ~(0xf << (index + 4)); + map &= ~(0xf << (index * 4)); /* For each base register. * Place the dimm size in 32 MB quantities in the bits 31 - 21.

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答复: AMD K8 memory bug with more than 2 banks
by YhLu 18 Mar '04

18 Mar '04

According to data sheet, should do the change. -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年3月18日 16:23 收件人: Craig C Forney 抄送: linuxbios(a)clustermatic.org 主题: Re: AMD K8 memory bug with more than 2 banks I have applied your fix and booted it up on a Tyan S2885 mainboard with four banks full, but have not noticed any change in non-reserved registers on the AMD 8111. Can you please elaborate on exactly what changes I might observe? I want to check out the specifications on the memory we're using and make sure we're getting the right values. On Tue, 16 Mar 2004, Craig C Forney wrote: > > I ran into a problem with a Dual Opeteron cPCI board we developed with 4 > banks of memory. It showed up when the third and fourth banks were > populated. I narrowed it down to a problem in src/amd/amdk8/raminit.c. > There is a '+' where there should be a '*', causing the SPD settings to > get corrupted, which causes bizarre results which varies depending on > the memory parameters read from the DIMMs. One possible result is that > some DIMMs will work marginally because one or more of their settings > has been corrupted. > > This patch seems to resolve the problem. I'm not sure if anybody else > out there is accessing 4 banks of memory via the Opteron memory > interface, so it might be just us, but it would probably be a good idea > to commit this patch to the freebios2 source tree. Can someone take > this on? > > Thanks, > > Craig Forney > Opus Innovations LLC > > diff -Naur raminit.c.orig raminit.c > --- raminit.c.orig 2004-03-16 13:25:05.000000000 -0800 > +++ raminit.c 2004-03-16 13:42:30.000000000 -0800 > @@ -924,7 +924,7 @@ > sz.side2 = 0; > } > map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); > - map &= ~(0xf << (index + 4)); > + map &= ~(0xf << (index * 4)); > > /* For each base register. > * Place the dimm size in 32 MB quantities in the bits 31 - 21. > > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios > _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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SST49LF008A-WH
by Victor Berdin 18 Mar '04

18 Mar '04

Hi, I checked the device list section but failed to find the mentioned chip. The closest one however is an SST49LF004. I would like to know if I can use Linux BIOS project in order to replace the original BIOSware? And if so, where can I start? My target board is an AMD GX2 Geode (NatSemi) SBC. `lspci -v` results are listed below. Any help/advice are greately appreciated. P.S., I really don't mind trashing this company hardware ;o) ... but it's best if I can make Linux work wonders on this device without killing innocent transistors. TIA and best regards - Vic ------------------ 00:01.0 Host bridge: National Semiconductor Corporation: Unknown device 0028 (rev 21) Subsystem: National Semiconductor Corporation: Unknown device 0028 Flags: bus master, 66Mhz, medium devsel, latency 248 I/O ports at ac1c [size=4] 00:01.1 VGA compatible controller: National Semiconductor Corporation: Unknown device 0030 (prog-if 00 [VGA]) Subsystem: National Semiconductor Corporation: Unknown device 0030 Flags: 66Mhz, medium devsel Memory at 41000000 (32-bit, non-prefetchable) [size=16M] Memory at 40ffc000 (32-bit, non-prefetchable) [size=16K] Memory at 40ff8000 (32-bit, non-prefetchable) [size=16K] Memory at 40ff4000 (32-bit, non-prefetchable) [size=16K] 00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C (rev 10) Subsystem: Realtek Semiconductor Co., Ltd. RT8139 Flags: bus master, medium devsel, latency 64, IRQ 11 I/O ports at ee00 [size=256] Memory at efffdf00 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 00:0f.0 ISA bridge: National Semiconductor Corporation: Unknown device 002b (rev 13) Subsystem: National Semiconductor Corporation: Unknown device 002b Flags: 66Mhz, medium devsel I/O ports at 6000 [size=8] I/O ports at 6100 [size=256] I/O ports at 6200 [size=64] I/O ports at 1000 [size=32] I/O ports at 9d00 [size=128] I/O ports at 9c00 [size=64] 00:0f.2 IDE interface: National Semiconductor Corporation: Unknown device 002d (prog-if 80 [Master]) Subsystem: National Semiconductor Corporation: Unknown device 002d Flags: bus master, 66Mhz, medium devsel, latency 0 I/O ports at eff0 [size=16] 00:0f.3 Multimedia audio controller: National Semiconductor Corporation: Unknown device 002e Subsystem: National Semiconductor Corporation: Unknown device 002e Flags: bus master, 66Mhz, medium devsel, latency 0, IRQ 11 I/O ports at ed80 [size=128] 00:0f.4 USB Controller: National Semiconductor Corporation: Unknown device 002f (rev 06) (prog-if 10 [OHCI]) Subsystem: National Semiconductor Corporation: Unknown device 002f Flags: bus master, 66Mhz, medium devsel, latency 0, IRQ 11 Memory at effff000 (32-bit, non-prefetchable) [size=4K] 00:0f.5 USB Controller: National Semiconductor Corporation: Unknown device 002f (rev 06) (prog-if 10 [OHCI]) Subsystem: National Semiconductor Corporation: Unknown device 002f Flags: bus master, 66Mhz, medium devsel, latency 0, IRQ 10 Memory at efffe000 (32-bit, non-prefetchable) [size=4K] ---------------

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答复: 答复: 答复: 答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64 [PMX:#]
by YhLu 18 Mar '04

18 Mar '04

Can you try by block instead of sector? YH -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年3月18日 13:16 收件人: YhLu 抄送: Li-Ta Lo; ron minnich; LinuxBIOS 主题: Re: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: flash_rom support for AMD64 [PMX:#] I should clarify that statement. The SST49LF040 part will flash with errors under 64-bit SuSE resulting in an unusable part. The PM part will flash properly in both 32-bit and 64-bit environments. On Thu, 18 Mar 2004, Hendricks David W. wrote: > Yes. The SST part will flash under 32-bit Gentoo, but not 64-bit SuSE. > > The PM part will flash using either 32-bit or 64-bit environments. > > On Thu, 18 Mar 2004, YhLu wrote: > > > Does it work in 32 bit? > > > > -----é‚®ä»¶åŽŸä»¶----- > > å‘ä»¶äºº: Hendricks David W. [mailto:dwh@lanl.gov] > > å‘é€æ—¶é—´: 2004å¹´3æœˆ18æ—¥ 13:06 > > æ”¶ä»¶äºº: YhLu > > æŠ„é€: Li-Ta Lo; ron minnich; LinuxBIOS > > ä¸»é¢˜: Re: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: flash_rom support for AMD64 > > > > I have verified this. > > > > The SST part still won't flash under 64-bit SuSE, however. > > > > On Thu, 18 Mar 2004, YhLu wrote: > > > > > It works with pm49lf004 under 64 bit. > > > > > > -----Ã“ÃŠÂ¼Ã¾Ã”ÂÂ¼Ã¾----- > > > Â·Â¢Â¼Ã¾ÃˆÃ‹: Li-Ta Lo [mailto:ollie@lanl.gov] > > > Â·Â¢Ã‹ÃÃŠÂ±Â¼Ã¤: 2004Ã„Ãª3Ã”Ã‚18ÃˆÃ• 11:50 > > > ÃŠÃ•Â¼Ã¾ÃˆÃ‹: YhLu > > > Â³ÂÃ‹Ã: ron minnich; Hendricks David W.; LinuxBIOS > > > Ã–Ã·ÃŒÃ¢: Re: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: flash_rom support for AMD64 > > > > > > On Thu, 2004-03-18 at 12:13, YhLu wrote: > > > > Stuck after 3. > > > > > > > > It seems it doesn't allow write mmio. > > > > > > > > int probe_49fl004 (struct flashchip * flash) > > > > { > > > > volatile char * bios = flash->virt_addr; > > > > unsigned char id1, id2; > > > > printf("3\n"); > > > > *(volatile char *) (bios + 0x5555) = 0xAA; > > > > myusec_delay(10); > > > > printf("4\n"); > > > > *(volatile char *) (bios + 0x2AAA) = 0x55; > > > > myusec_delay(10); > > > > printf("5\n"); > > > > *(volatile char *) (bios + 0x5555) = 0x90; > > > > > > > > > > > > > There is some arithmeatic error in old flash_rom, please > > > cvs update. > > > > > > Ollie > > > > > > _______________________________________________ > > > Linuxbios mailing list > > > Linuxbios(a)clustermatic.org > > > http://www.clustermatic.org/mailman/listinfo/linuxbios > > > > > > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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答复: 答复: 答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64
by YhLu 18 Mar '04

18 Mar '04

Does it work in 32 bit? -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年3月18日 13:06 收件人: YhLu 抄送: Li-Ta Lo; ron minnich; LinuxBIOS 主题: Re: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: flash_rom support for AMD64 I have verified this. The SST part still won't flash under 64-bit SuSE, however. On Thu, 18 Mar 2004, YhLu wrote: > It works with pm49lf004 under 64 bit. > > -----ÓÊ¼þÔ¼þ----- > ·¢¼þÈË: Li-Ta Lo [mailto:ollie@lanl.gov] > ·¢ËÍÊ±¼ä: 2004Äê3ÔÂ18ÈÕ 11:50 > ÊÕ¼þÈË: YhLu > ³ËÍ: ron minnich; Hendricks David W.; LinuxBIOS > Ö÷Ìâ: Re: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: flash_rom support for AMD64 > > On Thu, 2004-03-18 at 12:13, YhLu wrote: > > Stuck after 3. > > > > It seems it doesn't allow write mmio. > > > > int probe_49fl004 (struct flashchip * flash) > > { > > volatile char * bios = flash->virt_addr; > > unsigned char id1, id2; > > printf("3\n"); > > *(volatile char *) (bios + 0x5555) = 0xAA; > > myusec_delay(10); > > printf("4\n"); > > *(volatile char *) (bios + 0x2AAA) = 0x55; > > myusec_delay(10); > > printf("5\n"); > > *(volatile char *) (bios + 0x5555) = 0x90; > > > > > There is some arithmeatic error in old flash_rom, please > cvs update. > > Ollie > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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答复: 答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64
by YhLu 18 Mar '04

18 Mar '04

It works with pm49lf004 under 64 bit. -----邮件原件----- 发件人: Li-Ta Lo [mailto:ollie@lanl.gov] 发送时间: 2004年3月18日 11:50 收件人: YhLu 抄送: ron minnich; Hendricks David W.; LinuxBIOS 主题: Re: 答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64 On Thu, 2004-03-18 at 12:13, YhLu wrote: > Stuck after 3. > > It seems it doesn't allow write mmio. > > int probe_49fl004 (struct flashchip * flash) > { > volatile char * bios = flash->virt_addr; > unsigned char id1, id2; > printf("3\n"); > *(volatile char *) (bios + 0x5555) = 0xAA; > myusec_delay(10); > printf("4\n"); > *(volatile char *) (bios + 0x2AAA) = 0x55; > myusec_delay(10); > printf("5\n"); > *(volatile char *) (bios + 0x5555) = 0x90; > There is some arithmeatic error in old flash_rom, please cvs update. Ollie

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