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39714 discussions

17 Jan '05

You will create another member in dev? YH -----Original Message----- From: Li-Ta Lo [mailto:ollie@lanl.gov] Sent: Monday, January 17, 2005 5:18 PM To: YhLu Cc: Sagiv Yefet; LinuxBIOS Subject: RE: Running with VGA On Fri, 2005-01-14 at 20:59, YhLu wrote: > I add the code to amd_earlymtrr.c but found two problem > 1. in the cpu init, the second cpu cache can not be enabled. (still using > value set by amd_earlymtrr.c). ( before the amd_mtrr.c called by init). > 2. some slow in auto.c stage. Maybe because of before enable cache for > LinuxBIOS rom flash, there is more instruction to enable fixed mtrrs. > > So I prefer to two phase dev_init loop. > That is fine by me. How do you think put the ROM post into dev_post() and leave dev_init alone. Ollie > If you want me send the amd_earlymtrr.c with fixed mtrr enablement, please > let me know. >

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linkb_to_host and addon display adapter override onboard display card
by YhLu 17 Jan '05

17 Jan '05

linkb_to_host and addon display adapter override onboard display card committed. 1. linkb_to_host use bit 10 to find it if linkb to host. Please refer to in_coherent.c and hypertransport.c 2. Add vga_pri in device.c to make it = add on card instead of onboard vga, if add on card presents. Please refer to device.c and pci_rom.c YH

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print_spew() question
by Stephen.Kimball＠bench.com 17 Jan '05

17 Jan '05

I changed mainboard/vendor/board/Options.lb: ## Request this level of debugging output default DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging default MAXIMUM_CONSOLE_LOGLEVEL=9 Then I did a buildtarget, "make clean" and a "make". Then romcc complains that auto.c:3.0: macro DEFAULT_CONSOLE_LOGLEVEL already defined make[1]: *** [auto.inc] Error 1 How are you suppose to change the DEFAULT_CONSOLE_LOGLEVEL to get print_spew() to print? Regards, Steve Kimball Banchmark Electronics

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superio connected to the PCI bus?
by Andreas Bach Aaen (AH/TED) 17 Jan '05

17 Jan '05

Hi, can I from the lspci output see where the superio chips is connected? My lspci -tv says: lspci -tv -[00]-+-00.0 Intel Corp. E7501 Memory Controller Hub +-00.1 Intel Corp. E7000 Series Host RASUM Controller +-02.0-[02-04]--+-1c.0 Intel Corp. 82870P2 P64H2 I/OxAPIC | +-1d.0-[04]-- | +-1e.0 Intel Corp. 82870P2 P64H2 I/OxAPIC | \-1f.0-[03]--+-02.0 Intel Corp. 82546GB Gigabit Ethernet Controller | +-02.1 Intel Corp. 82546GB Gigabit Ethernet Controller | +-03.0 Intel Corp. 82546GB Gigabit Ethernet Controller | +-03.1 Intel Corp. 82546GB Gigabit Ethernet Controller | \-04.0 LSI Logic / Symbios Logic 53c1010 66MHz Ultra3 SCSI Adapter +-02.1 Intel Corp. E7000 Series Hub Interface B RASUM Controller +-1e.0-[01]-- +-1f.0 Intel Corp. 82801DB/DBL (ICH4/ICH4-L) LPC Bridge +-1f.1 Intel Corp. 82801DB/DBL (ICH4/ICH4-L) UltraATA-100 IDE Controller \-1f.3 Intel Corp. 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller The superIO chip is PC87417 which in linuxbios context probably would look a lot like tha allready supported PC8736[06] chips. I would help me a lot if some of your configuration scripts contained output from lspci, so you could see the coupling between the PCI bus description in your configuration language and the lspci format. Regards, -- Andreas Bach Aaen System Developer, M. Sc. Ericsson Telebit A/S tel: +45 89 38 51 00 Skanderborgvej 232 fax: +45 89 38 51 01 8260 Viby J Denmark andreas.b.aaen(a)ericsson.com

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compilation of tyan2735 linuxbios2
by Andreas Bach Aaen (AH/TED) 17 Jan '05

17 Jan '05

Hi, I am looking at a board chipsetwise a lot like the Tyan2735. When I compile tyan2735 I get the following problem from a few days old CVS shapshot: --------------- cp linuxbios_ram.nrv2b linuxbios_ram.rom echo "INCLUDE ldoptions" > ldscript.ld ; for file in /home/tedaba/linuxbios/x/freebios2/src/arch/i386/init/ldscript.lb /home/tedaba/linuxbios/x/freebios2/src//cpu/x86/16bit/entry16.lds /home/tedaba/linuxbios/x/freebios2/src//cpu/x86/32bit/entry32.lds /home/tedaba/linuxbios/x/freebios2/src//cpu/x86/32bit/reset32.lds /home/tedaba/linuxbios/x/freebios2/src//arch/i386/lib/id.lds ; do echo "INCLUDE $file" >> ldscript.ld ; done gcc -m32 -nostdlib -nostartfiles -static -o linuxbios -T ldscript.ld crt0.o /usr/bin/ld: section .reset [00000000fffdfff0 -> 00000000fffdffff] overlaps section .rom [00000000fffdc6eb -> 00000000fffe3e2f] /usr/bin/ld: section .id [00000000fffdffd9 -> 00000000fffdffef] overlaps section .rom [00000000fffdc6eb -> 00000000fffe3e2f] collect2: ld returned 1 exit status make[1]: *** [linuxbios] Error 1 make[1]: Leaving directory `/home/tedaba/linuxbios/x/freebios2/targets/tyan/s2735/s2735/normal' ---------------------- Can you see what's wrong in this configuration. I have actually ordered a tyan2735 board for testing, so I would really like to get this up and running. Regards, -- Andreas Bach Aaen System Developer, M. Sc. Ericsson Telebit A/S tel: +45 89 38 51 00 Skanderborgvej 232 fax: +45 89 38 51 01 8260 Viby J Denmark andreas.b.aaen(a)ericsson.com

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Re: HP Vectra VLi8 (intel 440bx)
by Richard Smith 15 Jan '05

15 Jan '05

On Sat, 15 Jan 2005 14:04:49 +0200, Mike Jackson <mj(a)sci.fi> wrote: > Richard Smith wrote: > > > send us a lspci -v and then look on the board and find out what > > superIO you have. You look good on the chipsets. The superIO will probally have a name like, ITE, NSC, SMC, winbond. It will probally be in a quad flat pack so its a rectangular surface mount chip with gull wing pins on all sides. The bios will either be a 32pin DIP or PLCC or perhaps a TSOP. the DIP is very rectangular and has pins that come out of the chip bend 90 degrees and then extend past the chip. What you normally think of for a chip. It either has to be mounted in holes or in a socket. The PLCC will be a square and will have pins on the side that are kinda shaped like a D. It can be surface mounted or have a socket. The TSOP will be very wide and flat with pins on the sides. Gull wing but they will be really small and close together. TSOP are really low profile. Itgoing to be surface mounted. If you can take a high res picture(s) of the board I can probally find them for you. -- Richard A. Smith

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Re: linuxbios on geode gx1.....
by Richard Smith 15 Jan '05

15 Jan '05

> my config looks as follows: >----- >target pcm-5823 >mainboard advantech/pcm-5823 Ah. Cool you are using V1 that will make things easier. I can't mess with this untill this weekend but I'll certainly give it a whirl. I was wanting to try and get linuxbios up on my reference platform anyway. One question though does your board have SDRAM or DDR? My reference boad has DDR soldered on the mainboard but looking at the raminit.inc code its not obvious if its for sdram or DDR. I've got the gx1533 reference board made by Via not by NSC. Dunno if they did anything differnt. -- Richard A. Smith

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Re: speaker beeper
by Adam Talbot 14 Jan '05

14 Jan '05

-Ron OK, so what would you advise is the next step. Where should I start looking/debugging. -Adam ----- Original Message ----- From: "Ronald G. Minnich" <rminnich(a)lanl.gov> To: "Adam Talbot" <talbotx(a)comcast.net> Sent: Friday, January 14, 2005 8:05 PM Subject: Re: speaker beeper > > > On Fri, 14 Jan 2005, Adam Talbot wrote: > > > The board is a Commell board, the LV-671 and embedded ITX system running a > > Pentium Mobile chip, with a 855GME Northbridge. > > "Is this as far as you've gotten?" I am VERY happy to now have some real > > out put to work with!! > > you're about where I am. The northbridge config is wrong :-( > > now we have to find out why. The northbridge is actually locking up, and > we have to see what it is we're not setting up correctly. > > ron >

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Is 440BX ported to Linuxbios v2?
by Svante Signell 14 Jan '05

14 Jan '05

Hello, I have been communicating with the Linuxbios mailing list on and off (mostly off lately). I'm interested to try out the linuxBIOS on my old dual CPU board MSI-6120. The current MSI/AMI BIOS V2.0 does not support newer CPUs than Coppermine. Currently I have two old PII processors (Mendocino) installed and would like to upgrade to one Celeron 2 or dual PIIIs (Tualatin) using one or two SLOT-T slot 1 to socket 370 adapters. A 1.3GHz Celeron 2 boots with this new CPU but runs _extremely_ slow, at aronund 8MHz compared to expected 1.3GHz. This has been reported before in the thread 'Level 2 cache activation code' in late 2003. Where can I purchase a replacement BIOS chip? Placed in a socket on the main board is a 2x16 pin DIL labeled: 686 AMI BIOS 1995 CS 92222. lspci shows: 0000:00:00.0 Host bridge: Intel Corp. 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) 0000:00:01.0 PCI bridge: Intel Corp. 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) 0000:00:07.0 ISA bridge: Intel Corp. 82371AB/EB/MB PIIX4 ISA (rev 02) 0000:00:07.1 IDE interface: Intel Corp. 82371AB/EB/MB PIIX4 IDE (rev 01) 0000:00:07.2 USB Controller: Intel Corp. 82371AB/EB/MB PIIX4 USB (rev 01) 0000:00:07.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02) 0000:00:0f.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone] (rev 30) 0000:00:10.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 05) 0000:00:10.1 Input device controller: Creative Labs SB Live! MIDI/Game Port (rev 05) 0000:01:00.0 VGA compatible controller: Matrox Graphics, Inc. MGA G400 AGP (rev 04) -- Svante Signell <svante.signell(a)telia.com>

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RE: Running with VGA
by YhLu 14 Jan '05

14 Jan '05

I check the amd_early_mtrr.c with old amd earymtrr.inc. It seems the only difference is not enable SYSCFG_MSR_MtrrFixDramModEn before clear MTRR fixed. I enable that, but the result shows no change.... YH

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